Advanced Encryption Standard For Smart Card Security

1
Advanced Encryption StandardFor Smart Card
Security

• Aiyappan Natarajan David Jasinski
• Kesava R.Talupuru Lilian Atieno
• Advisor Prof. Wayne Burleson

2
Outline

• Recap - Aiyappan
• System Interface - Aiyappan
• Key Expansion - David
• Encryption 1 - Lilian
• Encryption 2 Kesava
• Future Work Kesava

3
System Architecture
start
Reset
clk
Processor FSM
send
I/P FSM
Rdy_in
Reset
clk
clk
I/P
Key
128
Encrypt
Key Sched
1
Sub key
clk
128
O/P FSM
Data/Key Reg. Module
Reset
1
O/P
Ready O/P
Request O/P
4
Processor Finite State Machine

• The main controller for all the other modules
• Controlled by two signals Reset and start
• Gets instructions stored in the memory
• Decodes instructions
• Enables the appropriate signals

5
Input Controller

• Communicates with external system through a
  serial I/O pin
• Gets the input data and key from the external
  system
• Gives the 128-bit parallel data to data/key
  register module
• Controlled by processor

6
Data/Key register module

• Stores input data and key in the appropriate
  registers
• Controlled by processor through two control
  signals mux_en, d_k

7
Output Controller

• Sends the output data to the external system
• Controlled by processor
• Data transfer through serial I/O pin
• External communication through handshaking
  signals

8
Processor Input Controller Interface
PC
2
3
instr
9
Simulation Results
10
Simulation Results (contd.)
11
Processor - Output Controller Interface
clk
instr
PC
2
Processor FSM
3
Reset
sent
Output_data
Data_rdy
Output Controller FSM
128
External System
Encrypted Data
Send_data
clk
Serial I/O
12
Simulation Results
13
Work completed

• RTL code for all the modules
• Test bench for each module
• Simulation for each module
• Integrated the Processor , Data/key register,
  Input and Output controller
• Test bench for the integrated top module
• Simulation for the top module

14
Work to be done

• Integrate the Encryption core and Key scheduling
  core along with the interface
• Test Bench for the entire interface
• Synthesize each module
• Simulation for synthesized netlist
• Synthesize the total integrated module
• Simulation for the entire system

15
Key Expansion Outline

• Reminder of what Key Expansion is
• Update on the progress in this module
• Update on what still needs to be done

16
Key Scheduling

• Input 128 bit Key
• Output 1408 bit Expanded Key
• Process
• Word rotation
• Look up Tables
• XOR operations

17
Completed Work

• Behavioral Model (481 lines of verilog code)
• RTL code (422 lines of verilog code)
• Synthesized RTL code (30,000 gates)
• With warnings
• Error Propagation

18
Behavioral Functionality

19
Synthesized Design
20
Error Propagation
21
What Needs to Be Done

• Power Analysis
• Gate Level Timing Analysis
• Design Optimization

22
ShiftRow() Transformation
- 128 bit data is broken down into four
rows -Each of the 32-bit rows contains 4
bytes. -The first row is not shifted. -The last
three rows of the State are byte-wise cyclically
shifted as shown in the next slide.
23
no shift
24
- Operates on State column-by-column.- Each
column is treated as a four-term
polynomial.-The four bytes in the four rows
are used for matrix multiplication in GF(28) as
shown below.
Mix column() Transformation
25
BLOCK DIAGRAM FOR MIX COLUMN
Left shift by 1 bit
00011011
XOR
x1
XOR
26
Encryption Algorithm Flow
Raw Data
Sub Key
Key Add
Substitution
Shift Row
Mix Column
Key Add
Sub Key
Repeat (Round-1) times
Substitution
Shift Row
Key Add
ED
Sub Key
27
Sub_bytes Transformation
Input
8
8
8
8
8
8

S
S
S
S
S
S
8
8
8
8
8
8
Output
28
Add Round key Operation
Output
State
Key
A
B
C D
A1 B1 C1 D1
A2 B2 C2 D2
E F G H
E1 F1 G1 H1
E2 F2 G2 H2

I1 J1 K1 L1
I J K L
I2 J2 K2 L2
M N O P
M1 N1 O1 P1
M2 N2 O2 P2
29
State Diagram for Encryption
Algorithm
S0
Roll back to S0
Count1
S3
S1
Count2
S2
Count11
Repeat until Count 10
30
Future Work

• Integrate all modules
• Synthesize all modules
• Power Estimation for the integrated system
• Repeat all previous steps for the Decryption
  module