Advanced Encryption Standard For Smart Card Security

1
Advanced Encryption StandardFor Smart Card
Security

• Aiyappan Natarajan David Jasinski
• Kesava R.Talupuru Lilian Atieno
• Advisor Prof. Wayne Burleson

2
Outline

• Motivation
• System Architecture
• System Interface
• Encryption Core
• Key Scheduling
• Decryption Core
• Results
• Conclusion
• Future work

3
Motivation

• Security in Smart Cards - Cryptography
• Applications
• Identification Cards
• Credit Cards
• Algorithms Used
• Rijndael (Advanced Encryption Standard)
• DES(Data Encryption Standard)
• RSA(Ronald, Samir and Adleman)

4
System Architecture
128
128
Input Controller
Data/Key Reg
Encryption Core
128
External System
Processor
Key Scheduling
128
Output Controller
Decryption Core
128
Memory
Output data (From Enc/Dec core)
5
Processor Input Controller Interface
PC
2
3
instr
6
Processor Encryption Core Interface
clk
PC
2
Processor FSM
3
instr
Reset
encrypt
clk
Key Scheduling
Encryption Core
Cipher Text
128
128
Key_Out
clk
128
Input Data
7
Processor - Output Controller Interface
clk
instr
PC
2
Processor FSM
3
Reset
sent
Output_data
Data_rdy
Output Controller FSM
128
External System
Output data
Send_data
clk
Serial I/O
8
Encryption Algorithm Flow
Raw Data
Sub Key
Key Add
Substitution
Shift Row
Mix Column
Key Add
Sub Key
Repeat (Round-1) times
Substitution
Shift Row
Key Add
ED
Sub Key
9
Encryption Core
FF
128
Plain Text
CT
FF
clk
ARK
SB
SR
MC
clk
sel
cntrl
10
Sub_bytes (SB) Transformation
Input
8
8
8
8
8
8

S
S
S
S
S
S
8
8
8
8
8
8
Output
11
Add Round key (ARK) Operation
Output
State
Key
A
B
C D
A1 B1 C1 D1
A2 B2 C2 D2
E F G H
E1 F1 G1 H1
E2 F2 G2 H2

I1 J1 K1 L1
I J K L
I2 J2 K2 L2
M N O P
M1 N1 O1 P1
M2 N2 O2 P2
12
BLOCK DIAGRAM FOR MIX COLUMN
S0,C
S2,C
S3,C
S1,C
Left shift by 1 bit
8h1b
8h1b
8h1b
8h1b
XOR
x2
x2
x2
x2
x1
x3
x1
x3
x1
x3
x1
x3
XOR
S0,C
S1,C
S2,C
S3,C
13
Mix column() Transformation
- Operates on State column-by-column.- Each
column is treated as a four-term
polynomial.-The four bytes in the four rows
are used for matrix multiplication in GF(28) as
shown below.
14
Shift Rows (SR)
15
Encryption Simulations Result
16
Key Scheduling

• 486 lines of Verilog code (including 256 lines of
  a lookup table)
• Input 128 bit Key
• Output 1408 bit Expanded Key, sent out as four
  32 bit keys at a time
• Process
• Word rotation
• Look up Tables
• XOR operations

17
Block Diagram
clk
Mux_select
Key_In
clk
128
W_Out
128
128
128
Mux_select
Comb Logic
128
128
18
Decryption Algorithm Flow
Raw Data
Sub Key
Key Add
Inv Shift
Substitution
Key Add
Inv Mix
Sub Key
Repeat (Round-1) times
Inv Shift
Substitution
Key Add
PT
Sub Key
19
Decryption Core
Cipher Text
128
ARK
FF
ISR
key
128
sel
clk
ISB
ARK
PT
FF
128
IMC
clk
20
Decryption Simulation Results
21
Hierarchical Representation of the whole system
Processor FSM
I/P FSM
O/P FSM
Encrypt
Key Sched
Decryption
SB SR MC AR
ISB ISR IMC IAR
22
Synthesis with Synopsys

• Used a Virginia Tech Academic 0.25 um library
  (vtvtlib25.db)
• Input
• module.v files
• vtvtlib25 library
• Output module_gate.v files

23
Synopsys at Module Level
24
Floorplanning with Silicon Ensemble

• Input module_gate.v files and Virginia Tech LEF
  files
• Output module.gds2 files
• Sizes of 4 main modules
• Interface 760 um X 760 um
• Encryption Core 1095 um X 1095 um
• Decryption Core error in floorplanning
• Key Schedule 1800 um X 1800 um

25
Silicon Ensemble (Place Route)
26
Cadence Virtuoso (DRC Extraction)
27
Conclusions

• Hardware Implementation of the Rijndael algorithm
  using Verilog HDL
• Functional Verification of the code(1800) with
  the 384 test vectors for encryption/decryption
• Synthesis of Verilog Code
• Area Estimations

28
Future Work

• Optimize the system to accommodate different key
  and data lengths
• Delay and Power estimation
• Optimize the design in synthesis
• Verify using FPGA

29
References

• Draft of AES - Federal Information Processing
  Standards Publication, Washington D.C.
• Kuo, Henry and Ingrid Verbauwhede- Architectural
  Optimization for a 1.82Gbits/sec VLSI
  implementation of the AES Rijndael Algorithm
• Rankl and W.Effing- Smart Card Handbook, Second
  Edition, Chichester, England, John Wiley Sons
  Ltd.,2000