Critical Design Review (12/01)

1
Critical Design Review (12/01)

• Capital (Architecture Group)
• Theresa Baker
• Sudipto Chakraborty
• Jishnu Bhattacharjee
• Pranav Anbalagan

2
Requirements

• Define static processor, DSP Profiles, memory and
  bus architectures.
• Define interconnections between DLX and DSP
  processors while helping Data Path 2 group to
  develop switching scenarios.
• Determine bounds and reservation tables and work
  on applicable optimization issues.

3
Requirements...

• Help define decoders for DSP Profiles.
• Provide needed assistance during system testing.

4
Specifications

• Task Distribution
• Theresa Baker Static Processor (DLX), providing
  its code, helping software groups
  in compiling issues, website
  development, coordinating with SIS,
  SIH and DP2 groups.
• Sudipto Chakraborty Profile 1 and 2
  architectures, reservation tables,
  bounds, control path design,
  coordinating with Algorithm, DP1
  Decoder, and ISA groups

5
Specifications...

• Jishnu Bhattacharjee Profile 1 and 2
  architectures, reservation tables,
  bounds, control path design,
  coordinating with DP1, Decoder and
  ISA groups
• Pranav Anbalagan Profile 3 architecture,
  reservation tables, bounds, control
  path design, coordinating with
  DP1, Decoder and ISA groups

6
Specifications...

• Schedule
• 11/03/00 Profiles Picked, Static Processor
  Picked DLX .
• 11/08/00 Defined Hardware Profiles,Provided
  DLX Hardware Details,Provided details for
  DLX software tools.
• 11/10/00 Finalized DSP Hardware Details,
  Defined overall memory architecture

7
Specifications...

• 11/12/00 clear data and control flow issues
  with DP1 and decoder group
• 11/15/00 Reservation Tables for profiles1,2,3
  (with decoder group,ISA) , PDR, Web-site
• 11/27/00 determine bounds
• 12/01/00 CDR
• 12/06/00 Final Report, Final Design Review

8
Specifications

• Definition of the profiles
• Profile 1 IDCT
• Profile 2 VLD, RLD, Inverse Quantization,
  Inverse Zigzag
• Profile 3 Motion Compensation
• Profiles 1 and 2 are modifications of
  Motorola-56k family with a Data Processor similar
  to ADSP2100. Profile 3 was kept similar to
  TMS320C6x architecture.

9
Specifications...

• Reasons for the choice of DLX
• DLX was chosen as the static processor since we
  already had the source code and the associated
  software tools available for it.

10
Specifications...

• Reasons for Profile Choices
• We looked at the C code provided by the algorithm
  group and determined the maximum parallelism that
  could be extracted.
• Given the time constraints of this project we
  were trying to keep each profile as simple as
  possible.
• We wanted to maximize the reusability of the code
  between the profiles and the DLX.

11
Specifications...

• For IDCT we are realized that a part of the code
  was similar to the FFT Butterfly and we used a
  Data Processor similar to the one given in our
  text that was described as being optimal for the
  Butterfly.
• Profile 2 was kept incrementally different from
  profile 1 as VLD, RLD etc do not require any sort
  of sophisticated computations.
• Profile 3 was chosen likewise since TMS320C6x
  architecture is highly efficient for motion
  compensation

12
Lessons Learned

• Schedule was met for all the tasks except bounds
  which is dependent on FSFGs which again may not
  be that much meanigful if we are going for fully
  sequential implementation
• Initially proposed architectures had to be
  altered to make them implementable in limited
  time tradeoff between optimization and quick
  implementation