Digital Integrated Circuits - week eleven -

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Digital Integrated Circuits- week eleven -

• Gheorghe M. Stefan
• http//arh.pub.ro/gstefan/
• - 2014 -

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3-Loop Digital SystemsProcessors
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Automata with intelligent registers

• DF-F
  JKF-F
• 0 -gt 0 0 00 or 01 0-
• 0 -gt 1 1 10 or 11 1-
• 1 -gt 0 0 01 or 11 -1
• 1 -gt 1 1 00 or 10 -0
• 0 -gt A A A-
• 1 -gt A A -A

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• The complex part of the circuit is reduced.
• Sometimes, the weight of the simple part
  increase.
• SDF-F / SJKF-F ?

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Comments on autonomy

• Why the complex part is reduced?
• Because each new loop closed in the system
  increases the autonomous behavior
• The first loop provides the autonomy of the state
• Te second loop provides the autonomy to evolve
• What kind of autonomy provides the third loop?

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Loop closed through memory
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The third loop simplified the sequencer instead
of a control automaton a command automaton is
used.
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Loop-coupled automata

• Maximal segregation between simple structure and
  complex structure
• Def. Processor loop-coupled a simple
  functional automaton with a complex control
  automaton.
• Def. Elementary processor the control
  automaton execute only one control sequence.

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Pixel correction revisited
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The control automaton
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Processor

• Composes loops functions performed by
  elementary processors
• Elementary computations instructions
• Instead of composing circuits, are composed
  instructions compositions in the symbolic
  domain
• Instruction set architecture (ISA) is an
  interface
• Performing instructions
• execute in one cycle
• interpret expanding in a sequence

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Harvard vs. von Neumann abstract model
(architecture)

• Harvard von Neumann
• abstract model abstract model

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An executing processor RISC
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RISC Reduced Instruction Set Computer

• Each instruction is executed in one clock cycle
• ISA includes only the most frequently used
  instructions
• Any complex instruction results as a sequence of
  RISC instructions

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External connections

• Data memory Program memory are directly
  connected only for simplicity. The good practices
  request pipelined of fully buffered connections.

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Facultative home work

• Problema 1 proiecta?i automatul finit din
  slide-ul Pixel correction revisited (slide 11).
  Sinteza plus simulare.
• Problema 2 proiecta?i sectiunea Control a
  procesorului toyRISC (vezi slide 16 si slide 21).
  Sinteza plus simulare.