Presentation for Advanced VLSI Course

1
Presentation for Advanced VLSI Course

• presented byShahab adin Rahmanian
• InstructorDr S. M.Fakhraie
• Major reference
• 3D Interconnection and Packaging
• Impending Reality or Still a Dream?
• ByEric Beyne
• December 2004

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Overview

• Introduction Why 3D-interconnects?
• Classification of 3D-technologies
• 3D-SIP
• 3D-SOC
• 3D-IC
• Conclusion

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Introduction Why 3D?

• Drivers for 3D interconnects packaging
• Size reduction
• minimal area/volume of an electronic system
• Solving the interconnect bottleneck
• Long interconnects are too slow
• Long interconnects consume too much power
• Hetero-integration
• Seamless mixing of different microelectronic
• technologies at the wafer level

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The Interconnect Bottleneck

• Driven by technology scaling, SOC devices are
• partioned in functional blocks (tiles)
• Within a tile
• Operations can be performed within a single
  clock cycle
• Interconnects Local and intermediate
  interconnect levels on
• the die
• The interconnect between the tiles
• Global interconnect levels longest on chip
  interconnect lines,
• significantly less interconnects than on
  local intermediate
• levels
• Speed-limiting factor on the chip require
  repeaters
• Significant source for area power consumption.

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The Interconnect Bottleneck

• If the functional tiles on the chip could be
  stacked in
• the 3rd dimensions, the chip area would be
  reduced,
• resulting in much shorter global interconnect
  lines.

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Logic Memory

• 2D interconnect
• Long lines between
• Logic Memory
• Through bus

• SOC solution
• Large die
• Large size
• Memory cells

3D interconnect Short, direct lines Between Logic
Memory banks
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3D-Interconnect technology

• Current developments in packaging technology
• are delivering the key enabling technologies for
• building true 3D stacked devices
• Thinning of wafers, below 50 µm , as thin as the
  active layer.
• Wafer-to-wafer bonding, up to 300 mm diameter
  wafers.
• Die-to-wafer bonding singulated top die are
  bonded to bottom
• die on a base wafer
• Wafer-through-hole technologies realization of
  electrically
• isolated connections through the silicon
  substrate.
• Many of these technologies were originally
  developed in
• the field of MEMS technology and are now finding
  their
• application in IC packaging technologies.

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Different 3D-interconnectflavors

• 3D-SIP 3D-System-in-a-Package
• Stacking of multiple die in a single package
• Stacking of multiple SIP-packages
• 3D-interconnects at the traditional chip pin-out
  level
• 3D-SOC 3D-System-on-a-Chip
• Stacking of wafers or die-to-wafer with
  3D-global
• interconnectivity at the tile-level
• 3D-IC
• Stacking of wafers with interconnectivity at
  local
• level (gate or transistor level)

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3D-SIPDie stacking in a single package

• Assembly by wire bonding of stacked die in a
  single
• package has been shown by several
  packaging vendors.
• Main limitation interconnectivity interposer
  substrate does
• not allow for complex rerouting among the
  die.
• Only possible for specific applications, such as
  standard
• memory stacking, or die with specific I/O
  pad rerouting.
• Requires Known-good-die(KGD)

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3D-SIPStacking of chip-scale SiP-packages

• Improving the Yield and manufacturability of
• 3D-SIP by stacking of 2D-SIP sub-systems
• Each layer is an SIP package
• Each layer has the same size
• Each layer is fully tested before final assembly
• Many different technologies may be used for each
• individual layer
• Results in
• Generic 3D technology
• Best yield and manufacturability
• Limitations
• Relatively low 3D interconnectivity
• Lack of standardization of package sizes

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3D-SIP visionary applicationE-cube

• E-Cube distributed, fully autonomous system for
• realizing ambient intelligent systems.

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3D-SIP application Example

• 3D-SIP bluetooth rf radio, measuring
  7mmx7mmx2.5mm,
• Rf-front-end CSP stacked on a digital base band
  CSP.

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3D-SOC

• Stacking of die at the wafer level
• Reduced critical global interconnect lengths by
• stacking
• 3D-interconnectivitiy at the tile level
• Requires a significantly higher 3D-wiring
  density than
• 3D-SiP
• Technology components
• Die-to-wafer transfer bonding different
  chip sizes allowed
• Uses very thin Si 50 µm and below

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Ultra Thin Chip Stacking, UTCS

• Objective To Realize 3D-VLSI structures, based
  on the
• integration of thinned standard
  die, in a
• modified multilayer thin film
  technology

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3D Wiring scheme UTCS

• 3D interconnectivity around the perimeter of the
  die
• gt 100 connections per mm2 and per layer

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Wafer thinning

• 200 mm wafer CMOS wafer, thinned down to
• 50 µm thickness.

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Thinning of standard CMOSwafers, down to 10 - 15
µm
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Thinning of standard CMOSwafers, down to 10 - 15
µm
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Embedded test die
15 µm thin Si-die, transferred to a host
substrate and electrically connected to that
substrate
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Why ultra thin die thindielectrics ?

• Thermal thermal resistance dielectrics between
• die in the stack result in an increase of
  the
• thermal resistance
• 1 µm BCB dielectric 10 µm SiO2 1 mm Si
• 10 µm BCB between two 1 cm2 die 0.5 K/W
  thermal resistance
• Interface thermal resistance Die/BCB
• for 1 cm2 die 0.3 to 0.75 K/W (experimental)
• Mechanical thermo-mechanical stress limits the
• maximum height of the stack to 3 layers.

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Why ultra thin die thindielectrics ?

• Electrical thin dielectrics allow for a tighter
• interconnect line pitch for the same cross-talk
  level

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Impact of wafer thinning on theelectrical
performance

• Test chip 20x20 mm, IMEC 0.35 µm CMOS
• process development test reticle.
• Processing
• Mechanical wafer thinning down to 50 µm
• Face-down bonding test wafer to a dummy carrier
  wafer
• Plasma thinning test die down to 10-15 µm
• Singulation die
• Transfer of thinned die to a carrier substrate
• Measurements Transistor parameters before
• and after thinning.

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Electrical measurements

• Vtlin versus Ldes for CMOS transistors, measured
  before
• and after thinning and stacking on a host Si
  wafer.

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3D-IC3D-local interconnects at gate-level

• Scaling-driven technology integrates more
  transistors per unit area.
• Differences with 3D-SOC
• 3D-interconnects are local interconnects
  several orders
• of magnitude more connections required
  than 3D-SOC.
• 3D-interconnects block substantial areas for
  transistor
• logic lower effective integration density
• No solution for long, global interconnect lines
• Requires wafer-to-wafer bonding equal size
  stacked die.
• Highly complex technology, questionable yield
  economics

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Conclusions

• In order to be successful, 3D-Interconnect and
• packaging technologies need to become
• manufacturable technologies (high yield)
• high degree of parallel processing of individual
  layers,
• testing of these intermediate layers
• stacking of known-good-devices.
• This goal is likely to be reached first for
  3D-SIP,
• followed by 3D-SOC.
• This is confirmed by the emergence of such
• technologies in actual products.
• It is much further out for 3D-IC technologies.

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References

• 1 Eric Beyne 3D Interconnection and Packaging
  Impending Reality or Still a Dream?ISSCC 2004
• Pictures from Reference 1
• 2 G.Carchon et.al., IEEE-CPMT, vol. 24, pp.
  510-519, 2001.