CS M51A/EE M16 Winter

1
CS M51A/EE M16 Winter05 Section 1 Logic Design
of Digital SystemsLecture 17 - Grande Finale
March 16

• Yutao He
• yutao_at_cs.ucla.edu
• 4532B Boelter Hall
• http//courseweb.seas.ucla.edu/classView.php?term
  05Wsrs187154200

2
Outline

• Breaking News
• Chapter 12
• Read-Only Memory (ROM)
• The Class Review
• The Final Review and Sneak Preview
• Course evaluation

3
Breaking News

• Good News
• No more homework
• No more projects
• No more quizzes
• No more midterms
• No more deadlines
• No more lectures
• Bad News
• No more jokes
• The Final on Friday

4
Read Only Memory (ROM)
E
n
Address Inputs
2n x k ROM
k
Outputs
5
ROM Implementation
6
Types of ROMs

• Mask-programmed ROM
• Programmable ROM (PROM)
• Erasable Programmable ROM (EPROM)
• Electrically Erasable Programmed ROM (E2PROM)
  (aka flash memory)

7
Design Comb. Systems Using ROMs

• Basic facts
• a combinational circuit
• stores the entire truth table of switching
  functions
• a non-volatile memory
• the stored data wont disappear with the power
  off
• Basic Steps
• 1. Obtain the truth table
• 2. Decide size of ROMs (n, k)
• 3. Program (copy) the entire truth table into
  the ROM
• 4. Enable the ROM

8
Example Design A 1-bit Full Adder

• Need one 8 x 2 ROM

9
A 1-bit Full Adder (Contd)
1
10
Design Seq. Systems with ROMs

• Basic Steps
• 1. Obtain the state transition table
• 2. Decide size of ROMs (n, k) and state registers
• 3. Program (copy) the entire transition table
  into the ROM
• 4. Connect the ROM and state registers properly
• 5. Enable the ROM
• 6. Hook up the clock signal to the register

11
Example A Modulo-3 Counter
x
Modulo-3 Counter
y1 y0
CLK

• Need
• one 8 x 2 ROM
• one 2-bit register

12
A Modulo-3 Counter (Contd)
1
13
Analysis - Ex.12.12
0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1
0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 1 0 0 1
14
Big Picture of CSM51A/EE16
Idea
Specification
Logic Design
Physical Design
Fabrication
15
Big Picture of CSM51A/EEM16 ( Contd)
16
Big Picture of CSM51A/EE16 (Contd)
17
Historic Milestones

• On Dec. 23, 1947, the 1st transistor is developed
  in the Bell Lab
• On July 20, 1959, the patent application for IC
  technology is filed
• In 1968, Intel is founded by R. Noyce, A, Grove
  and G. Moore
• In 1971, the 1st ?PC - Intel 4004 was born in
  Intel
• In 1982, Time names the computer as its Man of
  the Year
• In 2004, Intel announces Pentium 4 ?PCs at 3.4GHz
• In 2017, physical limit of the current technology
  will be reached.
• What about after 2017?

18
Final Logistics

• Date and Time
• 8-11am
• March 18 (Friday), 2005
• Location
• Knudsen 1220B
• My Extra Office Hour
• March 17 (Thursday) 730-9pm 4750 BH
• Rules
• Closed-book/Closed-note w/ one 4-page single-side
  cheat sheet
• Calculator is allowed
• Coverage
• Chapters 1 - 12, and Handout Note 1

19
Material Wont Be Tested

• uVHDL 2.6, 3.11, 4.5, 7.9, 8.11
• Power dissipation and noise margins 3.5
• Carry-Lookahead Adder part of 10.1, part of 10.2
• ALU Networks part of 10.4
• Comparator Networks10.5
• Networks with standard arithmetic modules10.7
• Timing analysis of sequential systems 8.4
• Networks of counters part of 11.3
• Multimodule systems 11.4
• Networks of ROMs part of 12.2
• 12.1, 12.3-12.5

20
The Final Sneak Preview

• Philosophy
• Test your theoretical and hands-on fluencies in
  logic design of digital systems
• Scope
• Accumulative but focus on the materials after the
  midterm
• Length
• Will have about 9-10 problems
• Format
• Q A

21
Incomplete Checklist for the Final

• Important topics before Midterm
• Specification of combinational systems
• Minimization of combinational systems
• Arithmetic operations
• Arithmetic modules
• Basic topics on sequential systems
• Specification
• word problems
• State Minimization
• Design w/ FFs
• state assignment
• Analysis
• debugging

22
Incomplete Checklist for the Final

• Chapters 9, 11 and 12
• Decoders/Encoders, MUXes/DEMUXes
• Registers, Shifter Registers, and Counters
• ROMs
• Combinations of the above

23
Advice

• You dont have to memorize everything
• Make good use of the cheat sheet
• Make sure to go over all examples in my lecture
  notes
• Make sure to go over all homework problems and
  quizzes
• Study even harder and sleep even better
• Calm down and read the problem CAREFULLY

24
Rehearsal Problems

• Design a D FF with a JK FF and gates
• Analysis
• Ex. 11.21
• Design a sequential system w/ Mod-16 counter
• Quiz 4

25
Rehearsal Problem 1

• Design a D FF with a JK FF and AND, OR, NOT gates

26
Rehearsal Problem 1 - Cont.
D(t) 0- 1--1 -0JK
27
Rehearsal Problem 1 - Cont.
28
Rehearsal Problem 2

• Analysis
• Ex. 11.21

29
Rehearsal Problem 3

• Using a modulo-16 counter, implement a counter
  with the following periodical sequence
• 0, 2, 5, 6, 7, 9, 10, 12, 13, 15

x
x
30
Rehearsal Problem 3 - Cont.
x 0
x 1
S3 S2 S1 S0 I3 I2 I1 I0 TC
S3 S2 S1 S0 I3 I2 I1 I0 TC
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0
0 0 0 1 - - - - -
0 0 0 1 - - - - -
0 0 1 0 0 0 1 0 0
0 0 1 0 0 1 0 1 0
0 0 1 1 - - - - -
0 0 1 1 - - - - -
1 1 1 1 1 1 1 1 0
1 1 1 1 0 0 0 0 1
31
Wish You Best of Luck!!!!
32
Summary

• So long