CS M51A/EE M16 Winter

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CS M51A/EE M16 Winter05 Section 1 Logic Design
of Digital SystemsLecture 7
February 2

• Yutao He
• yutao_at_cs.ucla.edu
• 4532B Boelter Hall
• http//courseweb.seas.ucla.edu/classView.php?term
  05Wsrs187154200

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Outline

• Chapter Wrap-up Programmable modules
• Chapter 6 Multiple-Level Networks
• Summary

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Design in Two-Level Logic - Review

• Basic Technology
• AND-OR, OR-AND, NAND-NAND, NOR-NOR
• Programmable modules
• PLAs
• PALs
• Basic Skills
• K-Map
• Dont cares
• Minterms
• Maxterms
• Quine-McCluskey Algorithm
• Boolean Algebra

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Design with Programmable Modules

• Regular and standard structure
• Customized (programmed) for a particular function
• During the last stage of fabrication
• When incorporated into a system
• Flexible use and field upgrade
• Slower than fixed-function modules
• Common types
• PLAs
• PALs
• CPLDs
• FPGAs

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Programmable Logic Arrays (PLAs)

• Pre-fabricated building block of many AND/OR
  gates
• Programmed" by making or breaking connections
  among gates
• Programmable array block diagram for sum of
  products form

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Logic Diagram of PLAs

• All possible connections available before
  "programming"

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Alternative Representation

• Short-hand notation - don't have to draw all the
  wires

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How to design with PLAs

• Step 1
• Obtain the minimal AND-OR (Product-Of-Sum)
  expression of a function
• Step 2
• Construct the personality matrix
• Step 3
• Make connections on the logic diagram by placing
  a big dot at the corresponding cross-point.

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Design with PLAs - Example
A B C
F0 A B' C' F1 A C' A B F2 B' C'
A B F3 B' C A
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Programmable Array Logic (PAL)

• Each OR gate is connected to a subset of the AND
  gates

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Minimization of Multi-Output Functions

• Basic idea
• Separate each output function and minimize them
  individually
• Find out whether there is any common terms
  (product or sum) and share them if so.

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Two-Level Logic - Limitations

• One extra level is required if the complemented
  form of an input is not available
• Existing technologies limit the maximal number of
  inputs (fan-ins) of a gate
• Two-level implementation may require a large
  number of gates and an irregular structure
• The cost criteria of minimization is not adequate
  for many MSI/LSI/VLSI designs

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Design Using Multi-Level Logic

• Motivation
• To satisfy constraints
• network size
• number of gate inputs
• network delay
• Challenges
• No canonical form is available
• Several requirements have to be met
  simultaneously
• Several outputs have to be considered
• In reality, software CAD tools are used which
  employ heuristic algorithms to perform the
  minimization (Logic Synthesis)

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Design Procedure with Multi-Level Logic

• Step 1
• Obtain AND-OR or OR-AND expressions of switching
  functions of the system
• Step 2
• Transform expressions such that requirements are
  met
• Step 3
• Replace AND/OR gates with NAND or NOR gates
  whenever appropriate
• Several iterations may be needed

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Typical Transformation Techniques

• To reduce the network size
• Factoring
• abac a(bc)
• Sharing
• y abbc, z abbc
• Use other types of gates with small size
• XOR gates, etc.
• To reduce the fan-in of a gate
• term decomposition
• a b c d (ab) (cd)
• abcd (ab)(cd)
• To increase the output load of a gate
• Buffering

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Eg. 1 - 1-bit Comparator
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1-bit Comparator (Contd)
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1-bit Comparator (Contd)
Two-Level Networks - 7 AND gates - 4 OR
gates - 22 equivalent gates - 25 gate inputs
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1-bit Comparator (Contd)

• Applying transformation techniques
• z2 xyxc2yc2 xy(xy)c2
• z1 (xy)(xy)c1
• z0 xy(xy)c0
• Shared terms
• xy, xy
• Size
• 5 AND gates
• 4 OR gates
• 18 equivalent gates

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1-bit Comparator (Contd)

• Further Reduction
• Using NAND gates
• Size
• 9 equivalent gates

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Eg. 2 - Modulo-64 Incrementer
Two-Level Networks - 7 NOT gates - 20 AND
gates - 5 OR gates - 77 gate inputs
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Modulo-64 Incrementer (Contd)
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Modulo-64 Incrementer (Contd)
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Eg. 3 - Enabling Circuit
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Enabling Circuit (Contd)
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Design Using XOR Gates

• XOR Gates
• Exclusive OR, difference
• z x ? y xyxy
• Can be generalized into n inputs

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Eg. 5 - Parity-Checking Circuit

• Concept
• Error detection codes
• Additional bits are added for checking data bits
• Used extensively in data communication and
  storage
• Types
• Even
• The number of 1s is even
• Odd
• The number of 1s is odd

Data 0010 0001 Even 0010 0001 Odd 0010 0001
0 1
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8-Input Odd-Parity Checking Circuit

• High-Level Specification

• Two-Level AND-OR Implementation
• Too many gates

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Odd-Parity Checking Circuit (Contd)

• Design with XOR gates

• How to design an even-parity checking circuit
  using XOR gates?

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Eg. 7 - 32-bit Equality Comparator

• High-Level Specification

• Two-Level Implementation

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32-bit Equality Comparator (Cont.)
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Summary

• Programmable Modules
• PLAs and PALs
• Design combinational circuits using multi-level
  gate networks

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Next Lecture

• Chapter 4 Analysis of Combinational Networks