Memory II

1
Memory II

• Computer Architecture and Design
• Lecture 4

2
Target System Requirement

• There are many types of memories.
• The question What is the best memory? is
  invalid. The right question is What is the best
  memory for my application?.
• That means you have to understand the requirement
  of your target

3
IC vs. Board

• ICs (Integrated Circuit, Chip) can run at very
  high speed with more complex functions,
  typically.
• ICs design/fabrication cost is much higher,
  typically.
• Now lets think about what kind of memory you
  will prefer

4
Strengths and Weakness of Memories

• SRAMs
• Async. SRAM Read/Write operation finishes in
  access time. (Typ. access time is 6ns)
• Sync. SRAM Read/Write operation synchronized to
  clock signal.
• DRAMs
• SDR SDRAM Much higher density (meaning lower
  cost) than Sync. SRAM. High thruput due to burst
  transaction support.
• DDR SDRAM Thruput is even higher than SDR SDRAM
  because DDR supports burst transaction and double
  edge sampling. The chips using the external DDR
  should run twice faster than using external SDR
  to utilize the performance of DDR. Needs
  differential clocks. DDR cost is getting cheaper
  than SDR.

5
Burst Transaction

• Burst transaction means accessing multiple data
  in continuous address using pipelining.
• To setup start address and size for memrory,
  burst transactions need setup overhead of a few
  clock cycles.
• Programs and data (specially for multimedia
  application) are typically accessed by burst
  transactions these days. Why?

6
Flash Memory

• Nor flash is for simple applications. No burst
  transaction. Thruput lower compared to NAND
  flash. No access overhead due to pipelining for
  burst transactions as NAND does.
• Nand flash is for applications where massive
  storage or/and high thruput is required.
• Flash memory is typically implemented off-chip
  because on-chip flash is hard to implement and
  your dont have to include on-chip, typically.

7
Sync. SRAM Verilog Model

• module sram_16x8 (addr, clk, din, dout, we )
• parameter
• addr_width 4, word_depth 16,
  word_width 8
• input addr_width-10 addr
• input word_width-10 din
• output word_width-10 dout
• input clk, we
• reg word_width-10 mem 0word_depth-1
• reg word_width-10 dout
• always _at_(posedge clk) begin
• if(!we)
• memaddr lt dinword_width-10
• end
• always _at_(posedge clk) begin
• 1 dout lt memaddr

1
8
Homework 1

• Find the fastest commercial Async. SRAM and Sync.
  SRAM from websites. Compare their access times
  and latencies.

9
Verilog Homework 2
Use the synchronous SRAM as DUT and do the
simulation to write the data 0000 0000 0000
0001 0000 0010 . . 0000 1111 into the synchronous
SRAM from address 0 to address 15, and read the
content of the synchronous SRAM from address 0 to
address 15. Submit 1) DUT 2) testbench 3)
Simulation output waveform.