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Emery Berger

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Operating Systems CMPSCI 377 Lecture 2: OS & Architecture Emery Berger University of Massachusetts, Amherst – PowerPoint PPT presentation

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Title: Emery Berger


1
Operating SystemsCMPSCI 377Lecture 2 OS
Architecture
  • Emery Berger
  • University of Massachusetts, Amherst

2
Last Class Introduction
  • Operating system interface between user
    architecture

User-level Applications
virtual machine interface
Operating System
physical machine interface
Hardware
3
TodayOS Computer Architecture
  • Modern OS Functionality
  • Goals of Operating Systems
  • Hardware Support for OS Features
  • Architecture Basics Details

4
Modern OS Functionality
  • Provides support for
  • Concurrency
  • I/O Device Management
  • Memory Management
  • Files
  • Distributed Systems Networks

5
Concurrency
  • Supports multiple activities, apparently
    occurring simultaneously
  • Multiple users
  • Several users work as if each has private machine
  • Multiple processes/threads
  • One on CPU at a time
  • Multiple active concurrently

6
Modern OS Functionality, Cont.
  • I/O
  • CPU works while waiting on slow I/O devices
  • Memory Management
  • Coordinates allocation of RAM
  • Moves data between disk main memory
  • Files
  • Coordinates how disk space is used
  • Distributed Systems Networks
  • Lets group of PCs to work together on
    distributed h/w

7
Operating Systems Governments
  • Goals surprisingly like utopian political systems
  • Libertarianism
  • Socialism
  • Communism
  • OS researchers benevolent dictators

8
Libertarians
  • Infinite RAM, CPU
  • Protects users from each other

9
OS as Utopian Governments
  • Socialism
  • Safe secure communication
  • Protects everyone
  • Fair allocation of resources

10
Communism
  • To each according to his needs
  • Centralized control
  • Allocates resources efficiently (in theory)

11
Theory vs. Practice
  • Goals
  • Efficient fair resource allocation
  • Safe secure communication
  • Protect everyone from each other (isolation)
    from govt. (OS)
  • Illusion infinite RAM, CPU
  • But how can we do this efficiently?
  • Hardware support

12
Canonical System Hardware
  • CPU Processor to perform actual computations
  • I/O devices terminal, disks, video, printer
  • Memory data programs
  • System Bus Communication channel between above

13
Services Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
14
Protection
  • OS protects users from each other
  • Users cannot read or write other users memory
  • Name OSs that do and dont do this!
  • Protects self from users
  • Safe from errant or malicious users
  • Privileged instructions (e.g., halt machine)
  • Code data protected

15
Kernel ModePrivileged Instructions
  • CPU provides kernel mode restricted to OS
  • Inaccessible to ordinary users
  • Kernel core of operating system
  • Privileged instructions registers
  • Direct access to I/O
  • Modify page table pointers, TLB
  • Enable disable interrupts
  • Halt the machine, etc.
  • Indicated by status bit in protected CPU register

16
Protecting MemoryBase and Limit Registers
  • Hardware support to protect memory regions
  • Loaded by OS before starting program
  • CPU checks each reference
  • Instruction data addresses
  • Ensures reference in range

17
Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
18
Interrupts
  • Polling are we there yet? no! (repeat)
  • Inefficient use of resources
  • Annoys the CPU
  • Interrupt silence, then were there
  • I/O device has own processor
  • When finished, device sends interrupt on bus
  • CPU handles interrupt

19
CPU Interrupt Handling
  • Handling interrupts relatively expensive
  • CPU must
  • Save hardware state
  • Registers, program counter
  • Disable interrupts (why?)
  • Invoke via in-memory interrupt vector (like trap
    vector, soon)
  • Enable interrupts
  • Restore hardware state
  • Continue execution of interrupted process

20
Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
21
Traps
  • Special conditions detected by architecture
  • E.g. page fault, write to read-only page,
    overflow, system call
  • On detecting trap, hardware must
  • Save process state (PC, stack, etc.)
  • Transfer control to trap handler (in OS)
  • CPU indexes trap vector by trap number
  • Jumps to address
  • Restore process state and resume

22
Memory Traps
  • Special case trigger trap on write to protected
    memory area
  • Widely used in operating systems
  • Debugging
  • Distributed virtual memory
  • Approximating LRU
  • Garbage collection
  • Copy-on-write
  • Pay performance penalty only when needed

23
Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
24
Memory-Mapped I/O
  • Direct access to I/O controller through memory
  • Reserve area of memory for communication with
    device (DMA)
  • Video RAM
  • CPU writes frame buffer
  • Video card displays it
  • Fast and convenient

25
Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
26
Synchronization
  • How can OS synchronize concurrent processes?
  • E.g., multiple threads, processes interrupts,
    DMA
  • CPU must provide mechanism for atomicity
  • Series of instructions that execute as one or not
    at all

27
Synchronization How-To
  • One approach
  • Disable interrupts
  • Perform action
  • Enable interrupts
  • Advantages
  • Requires no hardware support
  • Conceptually simple
  • Disadvantages
  • Could cause starvation

28
Synchronization How-To, II
  • Modern approach atomic instructions
  • Small set of instructions that cannot be
    interrupted
  • Examples
  • Test-and-set (TST)if word contains given
    value, set to new value
  • Compare-and-swap (CAS)if word equals value,
    swap old value with new
  • Intel LOCK prefix (XCHG, ADD, DEC, etc.)
  • Used to implement locks

29
Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
30
Virtual Memory
  • Provides illusion of complete access to RAM
  • All addresses translated from physical addresses
    into virtual addresses
  • OS loads pages from disk as needed
  • Keeps track of which pages are in memory (in
    core) and which are on disk
  • Many benefits, including
  • Allows users to run programs without loading
    entire program into RAM
  • May not fit in entirety (think MS Office)

31
Translation Lookaside Buffer
  • First virtual memory systems performed address
    translation in software
  • On every memory access! (s..l..o..w..)
  • Modern CPUs contain hardware to do this the TLB
  • Hash-based scheme
  • Maps virtual addresses to physical addresses
  • Fast, fully-associative cache
  • Todays workloads are often TLB-miss dominated

32
Hardware Support
OS Service Hardware Support
Protection Kernel/User Mode Protected Instructions Base Limit Registers
Interrupts Interrupt Vectors
System Calls Trap Instructions
I/O Interrupts, Memory-Mapping
Synchronization Atomic Instructions
Virtual Memory Translation Lookaside Buffers
Scheduling Timer
33
Scheduling Timers
  • OS needs timers for
  • Time of day
  • CPU scheduling
  • Fairness limited quantum (e.g., 100ms) for each
    task
  • When quantum expires, switch processes
  • Uses interrupt vector

34
Summary
  • OS relies on hardware for many services
  • Protection
  • Interrupts
  • System Calls
  • Synchronization
  • Virtual memory
  • Timers
  • Otherwise impossible or impractically slow in
    software
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