Interconnect%20and%20Packaging%20Lecture%202:%20Scalability

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Interconnect and PackagingLecture 2 Scalability
Chung-Kuan Cheng UC San Diego
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Outlines

• Trends of Interconnect and Packaging
• Scalability
• References

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I. Trends of High Performance Interconnect and
Packaging
Year 2005 2010 2015
D1/2 Pitch nm 80 45 25
Chip size (mm2) 310 310 310
Pin count 3,400 4,009 6,402
Cents/pin 1.78 1.37 1.05
On-chip (MHz) 5,170 12,000 -
Off-chip (MHz) 3,125 - 29,103
Power Density (w/mm2) 0.54 0.64 -
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I. Trends

• On-Chip Interconnect
• Delay (5-40 times of Speed of Light 5ps/mm)
• Power Density (gt ½)
• Clock Skew Variations (5GHz)
• Off-Chip Interconnect and Packaging
• Number of pins (limited growth)
• Wire density (scalability)
• Speed and distance of interconnect

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I. Trends

• On-chip Global Interconnect trend
• Concerns Speed, Power, Cost, Reliability

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I. Trend

• Scalability
• Latency, Bandwidth
• Attenuation, Phase Velocity
• Distortion
• Intersymbol Interference, Jitter, Cross Talks
• Clock Distribution
• Skew, Jitter, Power Consumption
• IO Interface
• Density
• Impedance Matching
• Cross Talks, Return loops

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II. Scalability Interconnect Models

• Voltage drops through serial resistance and
  inductance
• Current reduces through shunt capacitance
• Resistance increases due to skin effect
• Shunt conductance is caused by loss tangent

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II. Scalability Interconnect Models

• Telegraphers equation

• Propagation Constant

• Wave Propagation

• Characteristic Impedance

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II. Scalability of Physical Dimensions

• R p /A p/(wt)
• Z ¼ (u/e)1/2 ln (bw)/(tw)
• C v Z
• L Z/v

p resistivity of the conductor u magnetic
permeability e dielectric permittivity v speed
of light in the medium
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II. Scalability of Physical Dimensions

• Resistance Increases quadratically with scaling,
  e.g. p2um-cm
• R0.0002ohm/um at A10umx10um
• R0.02ohm/um at A1umx1um
• R2ohm/um at A0.1umx0.1um
• Characteristic Impedance No change
• Capacitance per unit length No change
• Inductance per unit length No change

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II. Scalability of Frequency Ranges

1. RC Region
2. LC Region
3. Skin Effect
4. Loss Tangent

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II. Scalability of Frequency Ranges
1. RC Region
e.g. on-chip wires
R2ohm/um(A0.01um2) L0.3pH/um,
C0.2fF/um R/L0.67x1012
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II. Scalability of Frequency Ranges RC Region
Elmore delay model with buffers inserted in
intervals
ltr length from transmitter to receiver l
interval between buffers rn nmos resistance cn
nmos gate capacitance cg(1g)cn, g is pn
ratio. rw wire resistance/unit length cw wire
capacitance/unit length f cd/cg
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II. Scalability of Frequency Ranges RC Region
Elmore delay model with buffers inserted in
intervals
Optimal interval
Optimal buffer size
Optimal delay
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II. Scalability of Frequency Ranges
Example w 85nm, t 145nm
rn 10Kohm,cn0.25fF,cg2.34xcn0.585fF rw2ohm/um
, cw0.2fF/um
Optimal interval
Optimal buffer size
Optimal delay
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II. Scalability of Frequency Ranges RC Region
Year (On-Chip) 2005 2010 2015
rncn (ps) 0.86 0.39 0.18
rwcw (ps/mm) 284 616 1510
l (um) 168 77 33
D (ps/um) 0.096 0.095 0.101
no scattering, p2.2uohm-cm
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II. Scalability of Frequency Ranges RC Region

• Device delay, rncn, decreases with scaling
• Wire delay, rwcw, increases with scaling
• Interval, l, between buffers decreases with
  scaling
• In order to increase the interval, we add the
  stages of each buffer.

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II. Scalability of Frequency Ranges
2. LC Region
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II. Scalability
3. Skin Effect Skin Depth
e.g. 0.7um _at_ f10GHz, p2uohm-cm For
100umx25um RDC0.000008ohm/um 8ohm/m R
0.000114ohm/um114ohm/m
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II. Scalability
4. Loss Tangent
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References

• E. Lee, et al., CMOS High-Speed I/Os Present
  and Future, ICCD 2003.
• http//www.itrs.net/Common/2004Update/2004Update.h
  tm
• G.A. Sai-Halasz G.A. "Performance Trends in
  High-End Processors, IEEE Proceedings, pp.
  20-36, Jan. 1995.
• M.T. Bohr, Interconnect scaling-the real limiter
  to high performance ULSI Electron Devices
  Meeting, 1995., International10-13 Dec. 1995
  pp.241 244.