Trends%20and%20Perspectives%20in%20deep-submicron%20IC%20design

1
Trends and Perspectives in deep-submicron IC
design

• Bram Nauta
• MESA Research Institute
• University of Twente,
• Enschede, The Netherlands

IWORID 2002
2
Outline

• IC Technology trends
• Analog v.s. digital circuits
• How to design circuits in new technologies?
• Conclusion

3
IC Technology Trends
4
Moores Law Number of Transistors 80x86
Processors
5

The ITRS" Roadmap

98
2000
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
99
2001
(nm)


180
300
200
Volume Production
300
Volume Production
150
300
Volume Production
130
300
100
Basic steps/Modules
Volume Production
400 450
Integration/Pilot
Precompetitive
Basic steps/Modules
70
400 450
50
Advanced research (materials, architecture,..)
30
today
6
Supply Voltage Vdd

• Why Low Voltage?
• Low power digital
• No breakdown

today
2012
7
Threshold voltage VT
large Ion
Id
small Ioff
Vgs
Vdd
Ion
Ioff
Vss
OFF
ON
8
VT dilemma

• Sub-threshold leakage becomes problem
• low Idd during standby test -gt high VT
• fast switching -gt low VT
• dual VT
• Triple well (tune VT with voltage)

9
Transistor speed cut-off frequency
log Id/Ig
0
ft
Frequency
ft is about the intrinsic transistor, not
interconnect ft is a measure for the speed of
(analog) circuits
10
cut-off frequency
11
Example 30 nm Devices Intel
0.8 nm conventional SiO2(N)
30 nm physical gate length
mass production in 2009
12
Interconnect gt 6 metal layers
Intel
Transistor gate length 70 nm Metal-1 width
180 nm
13
Analog v.s. Digital Circuits
14
Power dissipation for analog processing
Vittoz, ISCAS 1990
independent of technology
15
Power dissipation for digital processing

• 1 bit extra -gt 6dB more S/N
• operations/sec n2. fsig

Vittoz, ISCAS 1990
depends on technology
16
Energy per transition
Etr10pJ for 4um 5V CMOS Etr1pJ for 1um 3V
CMOS (1990) Etr0.1pJ for 0.18um 1.8V
CMOS (2000) ????? ????? (2020)
17
downscaling lowers digital dissipation
analog
digital
Power dissipation
Signal/Noise dB
18
IC Technology scaling

• Optimized for digital
• digital main chip area
• minimize Etr
• minimize cost per transistor
• Analog has to live with this
• It cannot die

19
How to design circuits in new technologies?
20
Analog

• High voltage options for I/O EEPROM
• old transistors available in new technology
• Use the low VT
• needed for digital speed anyway
• non ideal device behavior
• gate leakage, non square law,
• no real problem, better models needed
• Nominal Vdd drops
• no stacking

21
Change analog circuits
VddVgs Vds
22
Analog

• matching of MOSFETS
• becomes better for same W.L
• new technology DVT drops linear with Vdd
• 1/f noise
• tends to increase for minimum size MOS

N
ft
ft
ft
f
23
1/f noise Reduction switched bias technique

• Constant Bias

Switched Bias Periodically switching the MOSFET
off
VON
VT
n-MOSFET
What about the Low-Frequency noise ?
24
1/f noise Reduction switched bias technique
LF noise spectrum (constant DC gate bias)
Expected noise spectrum of switched bias 6 dB
below (for 50 duty cycle)
Noise Power(dB)
Measured noise spectrum of switched bias gtgt6dB
below (for 50 duty cycle)
Frequency(log scale)
Switching frequency
25
analog RF passives components

• Inductors
• many metal layers high ohmic substrate
• high Q possible

top view
26
analog RF passives components

• C use fringe caps!

cross section view
27
Switched opamp technique
Vdd
Vdd
VsigVgs gt Vdd
Vsig
Vsig
Vgs
Peluso, JSSC, july 97
28
Analog strategy

• Exploit the speed
• feedback _at_ high frequencies
• noise canceling
• dynamic element matching
• sigma delta AD converters _at_ high frequencies
• Use digital for analog
• always digital on the chip
• use this for calibration, digital filtering

29
Digital

• transistor switching speed no issue
• low voltage but still too high power !!!
• leakage -gt dual VT
• but which VT where?
• how to manage complexity?
• 100M transistors
• interconnect is speed bottleneck

30
interconnect 1980
substrate
31
interconnect 1995
substrate
32
interconnect 2005
substrate
33
Digital / interconnect

• bottleneck wires
• repeaters, synchronizers
• globally asynchronous locally synchronous
• use analog for digital
• 3D microwave techniques
• nano modems ( more than just 1 and 0)

34
High-voltage digital I/O

• high voltage by design

5.5V I/O in 2.5V technology ! Annema,
JSSSC,March 2001
35
substrate bounce
Vdd
Lbondwire
substrate
36
substrate bounce
Vdd
Lbondwire
substrate
37
substrate bounce
Vdd
Lbondwire
substrate
38
substrate bounce

• Even 100 digital chip has problems
• Decouple supply in digital ( 30 area!)
• locally!
• Use package with low inductance
• Make very robust analog designs

39
Conclusion
40
conclusions

• Technology scaling gt 10 years
• Scaling of analog and digital circuits
  fundamentally different
• problems can be solved by design
• Digital for analog and analog for digital