Lecture 15: PCM, Networks

1
Lecture 15 PCM, Networks

• Today PCM wrap-up, projects discussion,
• on-chip networks background

2
Hard Error Tolerance in PCM

• PCM cells will eventually fail important to
  cause gradual
• capacity degradation when this happens
• Pairing among the pool of faulty pages, pair
  two pages
• that have faults in different locations
  replicate data across
• the two pages Ipek et al.,
  ASPLOS10
• Errors are detected with parity bits replica
  reads are issued
• if the initial read is faulty

3
ECP Schechter et
al., ISCA10

• Instead of using ECC to handle a few transient
  faults in
• DRAM, use error-correcting pointers to handle
  hard errors
• in specific locations
• For a 512-bit line with 1 failed bit, maintain a
  9-bit field to
• track the failed location and another bit to
  store the value
• in that location
• Can store multiple such pointers and can recover
  from
• faults in the pointers too
• ECC has similar storage overhead and can handle
  soft
• errors but ECC has high entropy and can hasten
  wearout

4
SAFER Seong et al., MICRO
2010

• Most PCM hard errors are stuck-at faults (stuck
  at 0 or
• stuck at 1)
• Either write the word or its flipped version so
  that the
• failed bit is made to store the stuck-at value
• For multi-bit errors, the line can be
  partitioned such that
• each partition has a single error
• Errors are detected by verifying a write
  recently failed
• bit locations are cached so multiple writes can
  be avoided

5
FREE-p Yoon et
al., HPCA 2011

• When a PCM block is unusable because the number
  of
• hard errors has exceeded the ECC capability, it
  is remapped
• to another address the pointer to this
  address is stored
• in the failed block
• The pointer can be replicated many times in the
  failed block
• to tolerate the multiple errors in the failed
  block
• Requires two accesses when handling failed
  blocks this
• overhead can be reduced by caching the pointer
  at the
• memory controller

6
Interconnection Networks

• Recall fully connected network, arrays/rings,
  meshes/tori,
• trees, butterflies, hypercubes
• Consider a k-ary d-cube a d-dimension array
  with k
• elements in each dimension, there are links
  between
• elements that differ in one dimension by 1 (mod
  k)
• Number of nodes N kd

(with no wraparound)
Number of switches Switch degree
Number of links Pins per node

N
Avg. routing distance Diameter
Bisection bandwidth Switch complexity
d(k-1)/2
2d 1
d(k-1)
Nd
2wkd-1
2wd
(2d 1)2
Should we minimize or maximize dimension?
7
Routing

• Deterministic routing given the source and
  destination,
• there exists a unique route
• Adaptive routing a switch may alter the route
  in order to
• deal with unexpected events (faults,
  congestion) more
• complexity in the router vs. potentially better
  performance
• Example of deterministic routing dimension
  order routing
• send packet along first dimension until
  destination co-ord
• (in that dimension) is reached, then next
  dimension, etc.

8
Deadlock Example
4-way switch
Input ports
Output ports
Packets of message 1 Packets of message
2 Packets of message 3 Packets of message 4
Each message is attempting to make a left turn
it must acquire an output port, while still
holding on to a series of input and output ports
9
Deadlock-Free Proofs

• Number edges and show that all routes will
  traverse edges in increasing (or
• decreasing) order therefore, it will be
  impossible to have cyclic dependencies
• Example k-ary 2-d array with dimension routing
  first route along x-dimension,
• then along y

1
2
3
2
1
0
17
18
1
2
3
2
1
0
18
17
1
2
3
2
1
0
19
16
1
2
3
2
1
0
10
Breaking Deadlock II

• Consider the eight possible turns in a 2-d array
  (note that
• turns lead to cycles)
• By preventing just two turns, cycles can be
  eliminated
• Dimension-order routing disallows four turns
• Helps avoid deadlock even in adaptive routing

West-First
North-Last
Negative-First
Can allow deadlocks
11
Deadlock Avoidance with VCs

• VCs provide another way to number the links such
  that
• a route always uses ascending link numbers

102
101
100
2
1
0
117
118
17
18
1
2
3
2
1
0
118
117
18
17
101
102
103
1
2
3
2
1
0
119
202
201
200
116
19
217
16
218
1
2
3
2
1
0
218
217
201
202
203

• Alternatively, use West-first routing on the
• 1st plane and cross over to the 2nd plane in
• case you need to go West again (the 2nd
• plane uses North-last, for example)

219
216
12
Packets/Flits

• A message is broken into multiple packets (each
  packet
• has header information that allows the receiver
  to
• re-construct the original message)
• A packet may itself be broken into flits flits
  do not
• contain additional headers
• Two packets can follow different paths to the
  destination
• Flits are always ordered and follow the same
  path
• Such an architecture allows the use of a large
  packet
• size (low header overhead) and yet allows
  fine-grained
• resource allocation on a per-flit basis

13
Flow Control

• The routing of a message requires allocation of
  various
• resources the channel (or link), buffers,
  control state
• Bufferless flits are dropped if there is
  contention for a
• link, NACKs are sent back, and the original
  sender has
• to re-transmit the packet
• Circuit switching a request is first sent to
  reserve the
• channels, the request may be held at an
  intermediate
• router until the channel is available (hence,
  not truly
• bufferless), ACKs are sent back, and
  subsequent
• packets/flits are routed with little effort
  (good for bulk
• transfers)

14
Buffered Flow Control

• A buffer between two channels decouples the
  resource
• allocation for each channel buffer storage is
  not as
• precious a resource as the channel (perhaps,
  not so
• true for on-chip networks)
• Packet-buffer flow control channels and buffers
  are
• allocated per packet
• Store-and-forward
• Cut-through

Time-Space diagrams
H
B
B
B
T
0 1 2 3
H
B
B
B
T
Channel
H
B
B
B
T
H
B
B
B
T
0 1 2 3
H
B
B
B
T
Channel
H
B
B
B
T
0 1 2 3 4 5 6 7 8 9 10 11 12 13
14 Cycle
15
Flit-Buffer Flow Control (Wormhole)

• Wormhole Flow Control just like cut-through,
  but with
• buffers allocated per flit (not channel)
• A head flit must acquire three resources at the
  next
• switch before being forwarded
• channel control state (virtual channel, one per
  input port)
• one flit buffer
• one flit of channel bandwidth
• The other flits adopt the same virtual channel
  as the head
• and only compete for the buffer and physical
  channel
• Consumes much less buffer space than cut-through
• routing does not improve channel utilization
  as another
• packet cannot cut in (only one VC per input
  port)

16
Virtual Channel Flow Control

• Each switch has multiple virtual channels per
  phys. channel
• Each virtual channel keeps track of the output
  channel
• assigned to the head, and pointers to buffered
  packets
• A head flit must allocate the same three
  resources in the
• next switch before being forwarded
• By having multiple virtual channels per physical
  channel,
• two different packets are allowed to utilize
  the channel and
• not waste the resource when one packet is idle

17
Example

• Wormhole

A is going from Node-1 to Node-4 B is going from
Node-0 to Node-5
Node-0
B
idle
idle
Node-1
A
B
Traffic Analogy B is trying to make a left
turn A is trying to go straight there is no
left-only lane with wormhole, but there is one
with VC
Node-2
Node-3
Node-4
Node-5 (blocked, no free VCs/buffers)

• Virtual channel

Node-0
B
Node-1
A
A
A
B
Node-2
Node-3
Node-4
Node-5 (blocked, no free VCs/buffers)
18
Buffer Management

• Credit-based keep track of the number of free
  buffers in
• the downstream node the downstream node sends
  back
• signals to increment the count when a buffer
  is freed
• need enough buffers to hide the round-trip
  latency
• On/Off the upstream node sends back a signal
  when its
• buffers are close to being full reduces
  upstream
• signaling and counters, but can waste buffer
  space

19
Router Pipeline

• Four typical stages
• RC routing computation the head flit indicates
  the VC that it
• belongs to, the VC state is updated, the
  headers are examined
• and the next output channel is computed (note
  this is done for
• all the head flits arriving on various input
  channels)
• VA virtual-channel allocation the head flits
  compete for the
• available virtual channels on their computed
  output channels
• SA switch allocation a flit competes for access
  to its output
• physical channel
• ST switch traversal the flit is transmitted on
  the output channel
• A head flit goes through all four stages, the
  other flits do nothing in the
• first two stages (this is an in-order pipeline
  and flits can not jump
• ahead), a tail flit also de-allocates the VC

20
Speculative Pipelines

• Perform VA, SA, and ST in
• parallel (can cause collisions
• and re-tries)
• Typically, VA is the critical
• path can possibly perform
• SA and ST sequentially

• Perform VA and SA in parallel
• Note that SA only requires knowledge
• of the output physical channel, not the VC
• If VA fails, the successfully allocated
• channel goes un-utilized

Cycle 1 2 3 4
5 6 7 Head flit Body flit 1 Body
flit 2 Tail flit
RC
VA SA
ST
RC
VA SA ST
--
SA
ST
SA ST
--
SA
ST
SA ST
--
SA
ST
SA ST

• Router pipeline latency is a greater bottleneck
  when there is little contention
• When there is little contention, speculation
  will likely work well!
• Single stage pipeline?

21
Title

• Bullet