MAPLD 2005 / 152

1
Assessing Application Performance in Degraded
Network Environments An FPGA-based Approach

• Mihai Ivanovici
• CERN, Geneva POLITEHNICA University, Bucharest
• Dr. Razvan Beuran
• CERN, Geneva POLITEHNICA University, Bucharest
• Dr. Neil Davies
• Predictable Network Solutions, Bristol

2
Outline

• Motivation
• Application performance assessment methodology
• Network emulator architecture
• Implementation considerations
• The hardware platform
• Experimental results
• Short-lived HTTP transfers over large delay
  connections
• Conclusions future work
• Acknowledgements

3
Motivation

• Rationale methodology for assessing the effects
  of network quality degradation on applications
• CERNs interest
• Long-distance networks have high costs ? must
  make an optimal use of resources
• What affects applications is not so much
  quality as the quality degradation (?Q)
  experienced
• This is something we can reproduce in the
  laboratory

4
Influence of quality degradation on application
outcome

• Interaction of Quality Degradation (?Q) and
  User-Perceived Quality (UPQ) for VoIP (G.711)
• Applications only care about the outcome, not the
  mechanisms

5
Networks Degraded Environments

• Assess application performance under varying
  network conditions

6
Assessing application performance

• Simultaneously
• Measure the network quality degradation (?Q)
• Assess the UPQ for the application under test

7
Reproducible controllable conditions

• Network emulation
• Hybrid technique that uses real applications
• Wide range of network conditions

8
The architecture
Replaceable modular components
9
Implementation philosophy

• Use of message passing
• Abstraction ? reusability independent module
  design
• Asynchronous concurrent processes (18)
• Use of Handel-C
• The concept of channels (CSP, Occam)
• Rapid development and translation into hardware
• Easy debugging due to channel-based architecture
• Flexible (custom) design
• Other projects GE tester, sniffers, traffic
  emulators

10
The hardware platform

• 1 Altera Stratix FPGA (25 k LEs)
• 2 GE PHYs
• 128 MB SDRAM
• 2 MB SSRAM
• 1 FLASH memory
• 3V3 PCI connector
• IP cores
• MAC IP core
• PCI controller
• SDRAM controller

11
Architectural choice SDRAM access
Direct access / semaphore Client / Server architecture
Inter-domain data transfers using channels are slow (4 cycles per word) Inter-domain data transfers using dual-port on-chip RAM are fast (1 cycle/word)
8-word burst SDRAM operations 8-word burst SDRAM operations
gt600 lines of code 300 lines of code
Achieved rate 400 Mb/s Achieved rate 1 Gb/s
12
The SDRAM Server
Channel selection Read 8-word bursts from
SDRAM 0 1 Confirm operation
completion Write 8-word bursts to SDRAM 0
1 Confirm operation completion

• while( 1 )
• prialt
• case sdram_read_request_channel ? operation
• par
• sdr0_read_burst8(memory_address,
  context)
• sdr1_read_burst8(memory_address,
  context)
• sdram_read_response_channel ! (unsigned 1)
  1
• break
• case sdram_write_request_channel ? operation
• par
• sdr0_write_burst8(memory_address,
  context)
• sdr1_write_burst8(memory_address,
  context)
• sdram_write_response_channel ! (unsigned 1)
  1

13
HTTP test results

• Site download duration vs. offered background
  traffic load

14
Current emulators

• Do exist
• Mainly software based
• Packet by packet systems
• Independent loss and delay applied to packets ?
  unrealistic behaviour
• False packet reordering
• Intra-stream contention not modeled

15
Why another emulator?

• More realistic scenarios
• Intra-stream and inter-stream contention
• Correlated loss and delay, natural induced jitter
• Phase / mode changes in network
• Topology or environment changes (e.g. wireless)
• More flexibility and control on the degradation
  models

16
Conclusions

• Methodology for assessing application performance
• Network emulator
• Use FPGA ? 1 G/s bidirectional
• High-accuracy operation
• Realistic effects through the use of intra- and
  inter-stream contention mechanisms

17
Future work

• Emulate multiple hops
• Implement server with vacations algorithms
• Aggregate models of queues and wires into one
  single model
• Build a new board
• Bigger and faster FPGA
• External (USB connected)
• Larger SDRAM

18
Acknowledgments

• Brian Martin and Jaroslav Pech for designing the
  board
• Matei Ciobotaru for implementing the low-level
  libraries for access to board components