LC3

1
Review for Final Exam
LC3 Controller FPGAs Multipliers Debounce
Circuit Basic Operation of N and P Type
FETs Logic Gates Built from FETs
2
Output Forming Logic
Input Forming Logic
Current State
LC-3 Datapath
3
Current State
Datapath Control
IFL
OFL
LC-3 Datapath
Next State
Datapath Status
4
Instruction Fetch

• 1. Copy PC contents to MAR
• enaPC 1 ldMAR 1

ldMAR
enaPC
ldPC
PC

• 2. Perform memory read
• selMDR1 ldMDR1

selPC
Increment PC selPC 00 ldPC 1

• 3. Copy memory output register contents to IR
• enaMDR 1 ldIR 1

selMDR
ALU
ldIR
IR
ldMDR
enaMDR
5
The Control Logic
aluControl
nzpMatch
enaMARM
memWE
selEAB1
selEAB2
selMAR
selMDR
enaMDR
enaALU
ldMDR
ldMAR
regWE
selPC
enaPC
SR2
SR1
ldPC
ldIR
DR
Flip Flops
OFL
IFL
Z
IR
N
P
6
The Fetch Cycle
Fetch0
enaPC ldMAR

1. PC ?MAR
2. PC ? PC1, MemMAR ? MDR
3. MDR ? IR

selPC lt 00 ldPC selMDR lt 1 ldMDR
Fetch1
Fetch2
enaMDR ldIR
7
A Note on Timing

• In all cases
• Buses are driven and muxes are selected during a
  state
• Registers and memory inputs are latched on the
  rising clock edge at the end of the state

8
Fetch 0 master loads during the last state of the
previous instruction
Fetch 0
Fetch 1
Fetch 2
F0 master loads
9
The contents of the PC are loaded into MAR
Fetch 0
Fetch 1
Fetch 2
PC contents are driven onto the Bus
10
The contents of the PC are loaded into MAR
Fetch 0
Fetch 1
Fetch 2
MAR and F1 masters load
11
Fetch Instruction into MDR / Increment PC
Fetch 0
Fetch 1
Fetch 2
Data is fetched from memory / PC is incremented
12
Fetch Instruction into MDR / Increment PC
Fetch 0
Fetch 1
Fetch 2
MDR, PC and F2 masters load
13
Load the instruction into the IR
Fetch 0
Fetch 1
Fetch 2
MDR contents are driven onto the Bus
14
Load the instruction into the IR
Fetch 0
Fetch 1
Fetch 2
IR master loads
15
The LEA Instruction
LEA
DR
1110
PCoffset9
selEAB1 lt 0 selEAB2 lt 10 selMAR lt
0 enaMARM DR lt IR119 regWE
LEA0

• RDR ? PC IR80
• Note that the PC Offset is always a 2s
  complement (signed) value

to Fetch0
16
The LDR Instruction
SR1 lt IR86 selEAB1 lt 1 selEAB2 lt 01
selMAR lt 0 enaMARM ldMAR
LDR0
LDR
DR
BaseR
0110
offset6
LDR1
selMDR lt 1 ldMDR

• MAR ? RBaseRoffset6
• MDR ? MemMAR
• RDR ? MDR

LDR2
enaMDR DR lt IR119 regWE
to Fetch0
17
The LDI Instruction
selEAB1 lt 0 selEAB2 lt 10 selMAR lt
0 enaMARM ldMAR
LDI0
LDI1
LDI
DR
1010
PCoffset9
selMDR lt 1 ldMDR
LDI2
enaMDR ldMAR

• MAR ? PC IR80
• MDR ? MemMAR
• MAR ? MDR
• MDR ? MemMAR
• RDR ? MDR

LDI3
selMDR lt 1 ldMDR
enaMDR DR lt IR119 regWE
LDI4
to Fetch0
18
The STR Instruction
SR1 lt IR86 selEAB1 lt 1 selEAB2 lt 01
selMAR lt 0 enaMARM ldMAR
STR0
STR
SR
0111
offset6
BaseR
SR1 lt IR119 aluControl lt PASS enaALU selMDR
lt 0 ldMDR
STR1

• MAR ? RBaseRoffset
• MDR ? RSR
• Write memory

STR2
memWE
to Fetch0
19
The STI Instruction
selEAB1 lt 0 selEAB2 lt 10 selMAR lt
0 enaMARM ldMAR
STI0
STI1
STI
SR
selMDR lt 1 ldMDR
1011
PCoffset9
STI2
enaMDR ldMAR

• MAR ? PC IR80
• MDR ? MMAR
• MAR ? MDR
• MDR ? RSR
• Write memory

SR1 lt IR119 aluControl lt PASS enaALU selMDR
lt 0 ldMDR
STI3
STI4
memWE
to Fetch0
20
The JSRR Instruction
JSRR
BaseR
enaPC DR lt 111, regWE
0100
0
000000
00
JSRR0

• Note Same opcode as JSR! (determined by IR bit
  11)
• R7 ? PC
• PC ? RBaseR

SR1 lt IR86 selEAB1 lt 1 selEAB2 lt 00
selPC lt 01ldPC
JSRR1
to Fetch0
21
FPGAs
22
Using ROM as Combinational Logic
B
C
F
A
C
schem1
A
B
C
lut1
F
tt1
23
Mapping Larger Functions To ROMs
LUT(CD)
B
C
D
f1
f2
F
B
C
D
A
Very similar to how we decomposed functions to
implement with MUX blocks
24
Mapping a Gate Network to LUTs
25
Mapping a Gate Network to 3LUTs
3LUT 2
3LUT 1
3LUT 3
26
Mapping Same Network to 4LUTs
4LUT 2
4LUT 1
27
FPGAs What Are They?
Programmable logic elements(LEs)
Programmable wiring areas
I/O Buffers
I/O Buffers
I/O Buffers
I/O Buffers communicatebetween FPGA andthe
outside world
I/O Buffers
An FPGA is a Programmable Logic Device (PLD)It
can be programmed to perform any function desired.
28
An FPGA Architecture (Island Style)
Column Wires
Row wires
Each LE is configured to do a function Wire
intersections are programmed to either connect or
not
29
Programmable Interconnect Junction
Column wire
ON
Connected
1
Row wire
Unconnected
OFF
0
30
Example Problem

• Generate the N, Z, P status flags for a
  microprocessor

Z
Z
N
P
D5
D0-D5
N
31
Example Problem

• Generate the N, Z, P status flags for a
  microprocessor

Z
Z
N
P
D5
D0-D5
N
Can be done with wiring only or with 1 4LUT
Will require 2 4LUTs
Will require 1 4LUT
32
N
1
2
3
4
5
D0
D1
6
7
8
9
10
P
D2
11
12
13
14
15
D3
D4
D5
LUT 1 F1 D0 D1 D2 D3 LUT 7 F2
F1D4D5 ? Z output LUT 8 F3 D5 ? N
output LUT 9 F4 Z N ? P output
Z
33
Configuring an FPGA

• An FPGA contains a configuration pin
• Configuration bits are shifted into FPGA using
  this pin, one bit per cycle
• Configuration bits in FPGA linked into a long
  shift register (SIPO)
• Examples on following slides ? conceptual
• Commercial devices slightly different

34
Structure of a 3LUT
b0
b1
b2
ConfigurationStorage Bits (Flip Flops)
b3
LUT Output
b4
b5
b6
Its just an 81 MUX LUT inputs select which
configbit is sent to LUT output Programming LUT
function ?setting configuration bits
b7
3
LUT Inputs
35
How are the Configuration Bit Flip Flops Loaded?
A serial-in/parallel-out(SIPO) shift
register These are the configuration
bitswhich the LUT selects from

b7
CONFIG
CLK

36
Configuring the Programmable Interconnect
Column wire
Configurationbit
b
Arranged in a SIPOshift register also
Row wire
37
Multipliers
38
Binary Shift/Add Multiplication
Add
Multiplicand
Result Shift Register
0
1
0
1
0
0
0
0
-
-
-
-
0000
1
0 1
Shift Register
0000
1
1
0
0
0101
Multiplier
Full Adder
0101
39
Binary Shift/Add Multiplication
Load
0101
Multiplicand
Result Shift Register
0
1
0
1
0
1
0
1
-
-
-
-
0000
0 1
Shift Register
1
1
0
0
Multiplier
Full Adder
0101
40
Binary Shift/Add Multiplication
Shift
Multiplicand
Result Shift Register
0
1
0
1
0
0
1
0
1
-
-
-
0000
0 1
Shift Register
1
0
0
-
Multiplier
Full Adder
41
Binary Shift/Add Multiplication
Add
Multiplicand
Result Shift Register
0
1
0
1
0
0
1
0
1
-
-
-
0000
1
0 1
Shift Register
0010
1
0
0
-
0101
Multiplier
Full Adder
0111
42
Binary Shift/Add Multiplication
Load
0111
Multiplicand
Result Shift Register
0
1
0
1
0
1
1
1
1
-
-
-
0000
0 1
Shift Register
1
0
0
-
Multiplier
Full Adder
0111
43
Binary Shift/Add Multiplication
Shift
Multiplicand
Result Shift Register
0
1
0
1
0
0
1
1
1
1
-
-
0000
0 1
Shift Register
0
0
-
-
Multiplier
Full Adder
44
Binary Shift/Add Multiplication
Add
Multiplicand
Result Shift Register
0
1
0
1
0
0
1
1
1
1
-
-
0000
0
0 1
Shift Register
0011
0
0
-
-
0000
Multiplier
Full Adder
0011
45
Binary Shift/Add Multiplication
Load
0011
Multiplicand
Result Shift Register
0
1
0
1
0
0
1
1
1
1
-
-
0000
0 1
Shift Register
0
0
-
-
Multiplier
Full Adder
0011
46
Binary Shift/Add Multiplication
Shift
Multiplicand
Result Shift Register
0
1
0
1
0
0
0
1
1
1
1
-
0000
0 1
Shift Register
0
-
-
-
Multiplier
Full Adder
47
Binary Shift/Add Multiplication
Add
Multiplicand
Result Shift Register
0
1
0
1
0
0
0
1
1
1
1
-
0000
0
0 1
Shift Register
0001
0
-
-
-
0000
Multiplier
Full Adder
0001
48
Binary Shift/Add Multiplication
Load
0001
Multiplicand
Result Shift Register
0
1
0
1
0
0
0
1
1
1
1
-
0000
0 1
Shift Register
0
-
-
-
Multiplier
Full Adder
0001
49
Binary Shift/Add Multiplication
Shift
Multiplicand
Result Shift Register
0
1
0
1
0
0
0
0
1
1
1
1
0000
0 1
Shift Register
-
-
-
-
Multiplier
Full Adder
50
Debouncer
51
Draw a State Graph
noisy
clrTimer
S0
noisy
noisytimerDone
noisy
S3
S1
noisytimerDone
noisytimerDone
debounced
noisy
noisytimerDone
noisy
S2
debounced clrTimer
noisy
52
An Improved State Graph
Looks like the FSMcan be implementedwith just a
single FF
noisy/clrTimer
Do you see why there is noneed for a reset input?
S0
noisytimerDone
noisytimerDone
noisytimerDone
S1
debounced
noisytimerDone
As mentioned, Mealymachines often requirefewer
states
noisy/clrTimer
53
Basic Operation of N and P Type FETs
N-Type FET
P-Type FET
S
S
S
S
G Vcc
G Gnd
D
D
D
D
S
S
S
S
G Gnd
G Vcc
D
D
D
D
54
Logic Gates Built from FETs
Logic Gate Implementation Using Field Effect
Transistors