241-440%20Computer%20System%20Design%20Lecture%206

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241-440Computer System DesignLecture 6

• Wannarat Suntiamorntut

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Part I Data Path (Multicycle)
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Whats wrong when CPI1
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Memory access time

• Physics
• Use hierarchy of memories

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Reduce the cycle time

• Cut combinational dependency graph and insert
  register or latch

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Partial the CPI 1
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Multi cycle datapath
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Flow with R-type instruction
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Flow with I-type instruction
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Flow with Load instruction
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Flow with Store Instruction
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Flow with Branch Instruction
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Minimizes Adder/ memory
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The control Model

• State specify control point for register transfer
• Transfer occurs upon exiting state

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Control Specification for multicycle
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Traditional FSM controller
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Map RT to Control Points
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Assign State
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Detail in Control Specification
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Controller Design

• Instructions have short sub-sequence.
• Use microsequencer
• microprogramming

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Jump counter
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Using Jump Counter
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Microsequencer
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Microprogram Control
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Summary

• Disadvantage of single cycle
• long cycle time
• cycle time is too long for all instructions
  except the load
• Multiple Cycle
• Divide instructions into small steps
• Execute each step in one cycle

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Next on Lecture 7