QuadCore Team

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QuadCore Team DLX ISA

• David Bild
• Greg Bok
• Jake Czyz
• Brandon Keao

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Floating-Point Instructions

• There are three categories for the DLX
  floating-point instructions
• Arithmetic
• Conversion
• Set-on-comparison
• All operation occur in the floating-point
  registers and are in the R-type format.

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DLX ISA

• Floating-Point Instructions Arithmetic
• Brandon Keao

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Floating-Point Instructions Arithmetic

• These intructions preform arithmetic operations
  on two floating-point registers
• Always R-format
• There are 2 categories of floating-point
  arithmetic instructions
• Single-precision
• Double-precision

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Floating-Point Instructions Arithmetic

• SP operations interpret the values in the two
  registers as SP FP values
• The result is rounded to a SP value and stored in
  a FP register
• ADDF- Adds two SP values
• SUBF - Subtracts two SP values
• MULTF - Multiplies two SP values
• DIVF - Divides two SP values

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Floating-Point Instructions Arithmetic

• DP operations interpret the values of two
  even/odd pairs of FP registers as DP FP values.
• The result if rounded to a DP value and stored in
  an even/odd pair of FP registers.
• ADDD - Adds two DP values
• SUBD - Subtracts two DP values
• MULTD - Multiplies two DP values
• DIVD - Divides two DP values

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DLX ISA

• Floating-Point Instructions Conversion
• And
• Special Instructions
• Greg Bok

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Floating-Point Instructions Conversion

• Sometimes need to convert between precisions or
  integer/floating-point
• The DLX ISA includes 6 such instructions
• R-format
• Double-precision FP register operands must be
  even-numbered FP registers
• 32-bit integers used

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Floating-Point Instructions Conversion

• CVT2DF double-precision to single-precision
• CVTD2I double-precision to integer
• CVTF2D single-precision to double-precision
• CVTF2I single-precision to integer
• CVTI2D integer to double-precision
• CVTI2F integer to single-precision

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Special Instructions TRAP

• J-type, unconditional branch
• 26-bit name field zero-extended to 32-bits to
  obtain target address
• Moves PC 8 to IAR (interrupt address register)

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Special Instructions RFE

• Return From Exception
• J-type, unconditional
• Returns to code that was executing before TRAP
  instruction
• Moves value in IAR register to PC

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Special Instructions NOP

• R-type
• Performs no operation -- hardware state is
  unaffected
• Typically used to fill branch delay slots when no
  useful instruction will work

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DLX ISA

• Floating-Point Instructions
• Set-on-Comparison
• David Bild

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Floating-Point Instructions Set-On-Comparison

• Compares two floating point numbers (SP or DP)
• Sets FPSR (Floating Point Status Register) to 1
  if comparison is true, 0 if false
• 6 comparisons are provided lt, gt, . lt, gt,

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DLX ISA

• Load Store Instructions
• Jake Czyz

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Load and Store Instructions

• For loading/storing data from/to memory
• Handle data of size
• Byte
• Halfword
• Word
• Double (for floating point only)

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Load and Store Instructions

• Byte and Halfword instructions always load/store
  the least significant byte or halfword,
  respectively.
• Loads and Stores may be done with any of the
  general purpose registers, except that loading R0
  has no effect (it always stores the value
  0x00000000).

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Load and Store Instructions

• All are I-Type

Bit 's 0 5 6 10 15 31
Opcode rs1 rd Immediate
Width 6 5 5 16

• Data always moved between memory and the
  register(s) specified by rd

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Load and Store Instructions

• Load/Store Address Calculations
• Load
• lw rd rs1 imm
• rd Mem(Sign_Extend(imm) rs1)
• Store
• sw rd rs1 imm
• Mem(Sign_Extend(imm) rs1) rd

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Load Instructions

• LB Loads a byte (w/ sign ext.)
• LBU Loads a byte (w/ zero ext.)
• LH Loads a halfword (w/ sign ext.)
• LHU Loads a halfword (w/ zero ext.)
• LW Loads a word

• LF Loads a single precision float
• LD Loads a double precision float
• to/from a pair of even/odd registers

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Store Instructions

• SB Stores a byte
• SH Stores a halfword
• SW Stores a word

• SF Stores a single precision float
• SD Stores a double precision float
• to/from a pair of even/odd registers

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Thank You