Power Estimation and Optimization for SoC Design

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Power Estimation and Optimization for SoC Design

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Outline

• Why low power for system design?
• How to design a low power system for SoC.
• Some power estimation tools.
• Conclusion
• Reference

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Power Driver Speed
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Power Limit Energy Density
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Impact of System Architecture
StrongARM RISC ARM ARMASIC ASIC ASIC (low power, 1v)
Performance 0.28s 1.12s 0.7s 10ms 46ms
Power 0.42J 0.62J 0.3J 0.63mJ 22.2uJ
Effort 1-2 weeks 1.5 weeks 2-4 weeks 9 months 15 months
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Design Flow of Low Power System
Specification
Architecture Design

High-Level Synthesis
Power Optimization
Power Gain
RT-Level
Power Analysis
Synthesis
Power Optimization
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Gate-Level
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Power Reduction Techniques

• Voltage Scaling Vcc reduction is the most
  effective way for reduction power.
• Leakage power is bigger factor.
• Exacerbate noise and reliability concerns.

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Power Reduction Techniques (cont.)

• Clock gating Reduce the switched capacitance on
  the clocks.
• Low power libraries Designed with power in
  mind.

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Power Reduction Techniques (cont.)

• Power-Delay curves the choice of logic family
  used can greatly influence the circuits power
  consumption.

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Power Reduction Techniques (cont.)

• Low power logic synthesis show 10 power saving
  for synthesis block.
• System power management monitor the system
  activity and enforce the movement of the system
  components between different power states.
• Software based power reduction CPU power
  consumption is dominated by a large cost factor
  (clock, caches, etc.) that for the most part,
  does not vary much from one cycle to the other.

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Power Estimation Tool JouleTrack

• Designed from MIT.
• A web based tool for software energy profiling.
• There are three order estimation
• First order Current consumption is independent
  of the code and depends only on the voltage and
  frequency.
• Second order Uses energy differentiated
  instruction.
• Third order Separate the leakage and switching
  energy components.

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Current Consumption of StrongARM SA-1100
Instruction Set
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Current consumption of 6 different benchmark
programs at different supply voltage and
frequency levels in the StrongARM
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First and Second Order Model Predictions Error
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JouleTrack Block Diagram
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Power Estimation Tool SimplePower

• Designed from Penn State University.
• A framework for evaluating the effect of
  high-level algorithmic, architectural, and
  compilation trade-offs on energy.
• It consists of the compilation framework and the
  energy simulator.
• Energy simulator is a five-stage pipeline
  datapath.

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Compilation framework of SimplePower
C Source Code
Assembly
Object file
SimpleScalar GCC
SimpleScalar GAS
SimpleScalar GLD
Executables
High Level Complier Optimizations
Low Level Complier Optimizations
Output Module
RT Level Optimizations
SimplePower
Energy Statistics
Core energy
Bus energy
Memory energy
I/O Pads energy
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Energy Simulator of SimplePower
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Power Estimation Tool PACT

• Designed from Northwestern University.
• Power-Aware Architecture and Compilation
  Techniques.
• Take an application written in the C programming
  language.
• Generate power-efficient and performance-efficient
  code for embedded system.

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The Architecture of PACT
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Conclusion

• Power consumption is a serious problem for SoC
  design.
• Techniques that have been tried on real designs
  in the past are described.
• Some power estimation tools which estimate the
  power consumption of embedded systems.

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Reference

• W. Fornaciari, P. Gubian, D. Sciuto, and C.
  Silvano, Power Estimation of Embedded Systems A
  Hardware/Software Codesign Approach, IEEE Tran.
  On Very Large Scale Integration (VLSI) Systems,
  Vol. 6, No. 2, pp.266-275, 1998.
• W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J.
  Irwin, The Design and Use of SimplePower A
  Cycle-Accurate Energy Estimation Tool, Design
  Automation conference, 2000.
• L. Benini, A. Bogliolo, and G. De Micheli, A
  Survey of Design Techniques for System-Level
  Dynamic Power Management, IEEE Tran. On Very
  Large Scale Integration (VLSI) Systems, Vol. 8,
  No. 3, pp.299-316, 2000.
• V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R.
  Patel, and F. Baez, Reducing Power in
  High-performance Microprocessors, 35th Design
  Automation conference, 1998.
• A. Sinha and A. P. Chandrakasan, JouleTrack A
  Web Based Tool for Software Energy Profiling,
  Design Automation conference, 2001.