A High Performance SoC: PkunityTM

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A High Performance SoC PkunityTM

• Chen Jie
• Peking University Microprocessor RD Center

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Contents

• PkUnity SoC Introduction
• PkUnity SoC Low Power Design

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Introduction
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PKUnity-3 Architecture
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UniCore fix-point processor

• UniCore Frequency 600MHz
• 32-bit harvard-architecture RISC CPU
• UniCore32 instruction set compatible
• Add conditional mov BLX instructions
• 8-stage instruction pipeline
• Dynamic prediction policy G-share
• Pipelined ID Cache
• Two-level TLB

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Performance Evaluation

• Unicore-II CPI increase 10-15
• G-share prediction, pipelined cache, two-level
  TLB reduce the increasing of CPI caused by deep
  pipeline
• UniCore-II MIPS increase 70- 80
• Performance improvement come from improvement of
  micro-architecture and technology

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SoC Design Platform

• To build
• a chip-based infrastructure
• a integrated develop environment
• a design and verification flow
• In PkUnity-3
• CPU configurable
• BUS configurable
• Interrupt system configurable
• DMA configurable
• Frequency configurable
• Power management

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Verification
Coverage-oriented VERA verification flow
SystemC-based HW/SW Co-verification methodology
FPGA prototype
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Contents

• PkUnity SoC Introduction
• PkUnity SoC Low Power Design
• Power research status
• PkUnity low power design and power estimation
• Future work

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Power New Challenge

• Power is a dramatic issue for SoCs with billions
  of transistors
• Power has to be reduced for portable devices that
  require a dramatic increase of computation power
• Deep submicron technologies (90 and 65 nm) will
  present a dramatic increase of leakage power
• Power still too high for most SoCs
• SoC Architectures, HW/SW, multiprocessor,
  multiple memories, are not well supported by CAD
  tools
• Reconfigurability and Flexibility compromises
  low-power
• Leakage and very low Vdd are dramatic problems

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LP Research Condition
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Power Estimation Research
Power Estimation Hierarchy
High level architectural model
SimplePower
simulation vs. analysis
Wattch
CACTI
simulation with timing info
extract circuit parameters adding technology
info gate level simulation
PrimePower
PowerCompiler
analysis with extractive parameter
HSPICE
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Power of Pkunity

• Embedded Processor High Performance vs. Low
  Power
• Three methods to reduce chip power
• Close unused module
• Frequency scaling
• Close Pll
• Pkunity-3 object
• CPU lt800mW_at_1.8V/600MHz
• SoC lt2000mW_at_1.8V/600MHz

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Power Estimation
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Power optimization

• Close unused module through gated clock
• Reduce chip power through scaling among multiple
  run mode
• Run
• Idle
• Sleep
• Change chip frequency through dynamic PLL
  configuration
• Input vector control in Execution components

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Work Flow
Low power design and estimation flow
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Future Work

• Power Estimation
• To pre-analyze arch micro-arch design through
  fast and accurate Architectural level power
  simulator
• To build a full-chip power simulator
• Power simulator parameter reconfigurable
• To build accurate leakage power estimation model
  
• Specific component power model

• Low Power Design
• Memory architecture (cache, TLB, register file)
• Clock system ( Syn vs. Asyn )
• Bus system
• Instruction set selection
• Voltage and frequency scaling
• Compiler optimization
• Task movement

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Thank you