EE 319K Introduction to Microcontrollers

1
EE 319KIntroduction to Microcontrollers

• Lecture 13 Serial Communications Interface
  (SCI), Producer-Consumer problems, FIFO Queues,
  Lab9

Read Book Sections 8.1, 8.2, 12.3.2, 12.3.3, 12.4
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Serial Comm. Interface (SCI)

• This protocol is also known as UART (Universal
  Asynchronous, Receiver Transmitter)
• Originally used to connect i/o terminals to
  mainframes.
• Neither fast nor reliable but simple

• SCI Device Driver
• Public routines
• SCI1_Init
• SCI1_InChar
• SCI1_OutChar
• Private Objects
• SCI1CR2
• SCI1BD
• SCI1SR1
• SCI1DRL

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SCI Basics

• Frame The smallest complete unit of serial
  transmission.
• Bandwidth The amount actual information
  transmitted per second.

• Baud Rate The total number of bits transmitted
  per secondbaud-rate 1/bit-time
• Mode Bit (M) Selects 8-bit(M0) or 9-bit (M1)
  data frames

A serial data frame with M0
number of information bits/frame

x baud-rate
Bandwidth
Total number of bits/frame
4
Transmitting in Asynchronous Mode
Data and shift registers implement the serial
transmission

• The software writes to SCI1DRL, then
• 8 bits of data are moved to the shift register
• start and stop bits are added
• shifts in 10 bits of data one at a time on TxD
  line
• shift one bit per bit time (1/baudRate)

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Receiving in Asynchronous Mode
Data and shift registers implement the receive
serial interface

• The receiver waits for the 1 to 0 edge signifying
  a start bit, then
• shifts in 10 bits of data one at a time from RxD
  line
• shift one bit per bit time (1/baudRate)
• start and stop bits are removed
• checked for noise and framing errors
• 8 bits of data are loaded into the SCIDRL

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SCI Details

• SCI1BD Determines the baud rate Say
  SCI1BD120 gt Integer BR
• SCI Baud-rate MClock/(16xBR)
• Mclock on 9S12DP512 is 24 MHz (with PLL in Load
  mode) 8 MHz otherwise.
• TE is the Transmitter Enable bit
• RE is the Receiver Enable bit.

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SCI Details

• TDRE is the Transmit Data Register Empty flag.
• set by the SCI hardware if transmit data register
  empty
• if set, the software can write next output to
  SCIDRL
• cleared by two-step software sequence
• first reading SCISR1 with TDRE set
• then SCIDRL write

• RDRF is the Receive Data Register Full flag.
• set by hardware if a received character is ready
  to be read
• if set, the software can read next input from
  SCIDRL
• cleared by two-step software sequence
• first reading SCISR1 with RDRF set
• then SCIDRL read

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SCI Details

• RIE is the Receive Interrupt Enable bit (Arm).
• set and cleared by software
• set to arm RDRF triggered interrupts
• clear to disarm RDRF triggered interrupts
• TIE is the Transmit Interrupt Enable bit (Arm).
• set and cleared by software
• set to arm TDRE triggered interrupts
• clear to disarm TDRE triggered interrupts

• SCI1DRL register contains transmit and receive
  data
• these two registers exist at the same I/O port
  address
• Reads access the read-only receive data register
  (RDR)
• Writes access the write-only transmit data
  register (TDR)

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SCI I/O Programming

• Initalize 9S12DP512 SCI at 38400 bps
• Inputs none
• Outputs none
• Errors none
• assumes 8 MHz E clock (PLL not activated)
• SCI1_Init
• movb 0c,SCI1CR2 enable SCI TERE1
• movw 13,SCI1BD 38400 bps
• baud rate(bps) 8000000/(16xBR) (38461.5)
• rts

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SCI I/O Programming
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SCI I/O Programming
Re-visit Tut3
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Overrun Error

• If there is already data in the SCI0DRL when the
  shift register is finished, it will wait until
  the previous frame is read by the software,
  before it is transferred. An overrun occurs when
  there is one receive frame in the SCI0DRL, one
  receive frame in the receive shift register, and
  a third frame comes into RxD.

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Tut2

• Busy-wait SCI input
• I/O bound (bandwidth limited to input rate)
• Very inefficient (spends a lot of time waiting)

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Tut2 Recover wasted time?

• Technique 1 Combine all busy-waits
• Requires cooperation,
• Complicated to test (all tasks are interrelated)
• Cant guarantee bound on latency

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Tut2 Recover wasted time?

• Technique 2 Input device interrupts when ready
• ISR reads new input, puts into FIFO
• Latency equals maximum time it runs with I1

FIFO queues and double buffers can be used to
pass data from a producer to a consumer
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FIFO Queues
Figure 12.6 FIFO queues can be used to pass data
between threads
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Tut4 Producer Consumer problem
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FIFO Two Implementations

• Differ in the way empty/full conditions are
  determined
• Two pointers (12.3.3, Tut4)
• Empty gt GetPt PutPt
• Full gt GetPt (PutPt1)buffer_size
• Wastes 1 buffer slot
• Two pointers with a counter
• Empty gt counter 0
• Full gt counter buffsize
• Uses all buffer slots

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FIFO Two Implementations

• Common to both Implementations
• GetPt Points to the data that will be removed on
  the next call to FiFo_Get
• PutPt Points to the empty space where the data
  will be stored on the next call to Fifo_Put
• Fifo_Put adds data at PutPt and increments PutPt
• FiFo_Get removes data at GetPt and decrements
  GetPt
• Wrapping must be handled because buffers are not
  infinite

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Wrap
Pointer wrap on 2nd put
Pointer wrap on 4th get
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Lab9
1.5 cm
1.50 cm
Figure 8.3 Data flows from the sensor through
the two microcontrollers to the LCD. The output
compare timer is used to trigger the real-time
sampling. Use the special serial cable to
connect the two SCI1 ports.
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Lab9
Communication interfacing between two 9S12
microcontrollers using SCI
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Simple Design
Courtesy Jon Valvano
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Issues in Lab 9

• Synchronization
• Blind-Cycle
• Busy Wait
• Interrupt
• FIFO
• Structured mechanism to pass data.
• Helps us cope with mismatched speeds of producer
  and consumer

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Lab 9 Transmitter

• Context Switch
• When a previously scheduled interrupt (OC
  interrupt) occurs, the processor has to switch
  context to run the corresponding ISR.
• What does this entail
• The current instruction (of the foreground
  process) is finished
• Push registers (including CCR) on Stack (with
  I0)
• Disable further interrupts (I1)
• Vector fetch and load ISR address into PC
• Demo in TExaS with Transmitter

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Lab 9 Transmitter

• When does the OC Interrupt occur?
• 3 conditions must be true
• Arm the Specific Interrupt (C0I1) - ritual
• Interrupts enabled (I0 using cli) - ritual
• Interrupt gets Triggered C0F is set when TCNT
  equals TC0
• What happens in ISR?
• Acknowledge Interrupt movb 01,TFLG1
• Read ADC data, encode, send one frame
• rti
• Note It is not necessary for you to set/clear
  the I bit except in the initial ritual, it is
  done automatically

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Lab 9 Receiver

• Context Switch
• When a scheduled interrupt (SCI RDRF interrupt)
  occurs, the processor has to switch context to
  run the corresponding ISR.
• When does the SCI RDRF Interrupt occur?
• 3 conditions must be true
• Arm the Specific Interrupt (RIE1) - ritual
• Interrupts enabled (I0 using cli) - ritual
• Interrupt gets Triggered RDRF is set when a new
  frame arrives
• What happens in ISR?
• Acknowledge Interrupt By reading SCI0SR1 and
  SCI0DRL
• Read a frame and pass to foreground through
  global memory Schedule
• rti

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Lab 9 Why FIFO?

• May use unstructured globals to pass data
• Is there data in there?
• Are you writing new data overtop old data?
• Are you reading garbage?
• FIFOs are structured globals
• Fifo_Put stores data Fifo_Get retreives data
• First in first out means the data remains in
  order
• Real way to implement thread synchronization
• The producer needs to stall if FIFO is full
• The consumer needs to stall if FIFO is empty
• Lab7 way to implement thread synchronization
• The producer throws data away if FIFO is full
• The consumer waits if FIFO is empty

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Lab9 Receiver Main program

1. Initialize Timer, LCD, Fifo_Init, SCI
2. Fifo_Get (wait here until data is available)
3. Convert from 8-bit sample to decimal fixed-point
4. Display on LCD
5. repeat 2,3,4 over and over

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Interrupt Programming