Physical Design and Spatial Optimization

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Physical Design and Spatial Optimization

• Igor Markov
• Advanced Computer Architecture Lab
• University of Michigan

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Logistics of Computer Chips

• Complexity billions of transistors
• Each needs power
• Each needs physical space
• Each communicateswith other transistors
• Geometry
• On-chip distances are large(vs single transistor
  size)
• Communication is expensivewires do not scale as
  well as transistors
• Difficult landscape fixed obstacles (caches,
  IP), power/ground lines, fixed I/O ports,
  area-array I/Os, etc

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Handling Communication Complexity
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• Divide and Conquer Partitioning
• Automatic place-and-route
• Optimize global placement (500K modules/hour)to
  minimize communication delays
• Optimize routing (for data signals clock
  distribution)
• All at the same time on-going work
• Giving up global synchronization
• Dozens of local clock domains
• Different frequencies possible (to save power)
• Simultaneous optimization across multiple domains

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Spatial Clusters and Hierarchies

• Consider large macro formations,rather than
  single devices
• Select types, synchronize, place, route, test,
• Shapes and sizes become more important

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Geometry Optimization

• Optimize spacing between objects
• Improve communication delays
• Keep congestion low

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Reducing Communication Delay

• After placement is available,automatically
  rewire existing communications to improve delays

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Recent Work

• SCAMPI SCalable Advanced Macro- Placement
  Improvements
• Variety of macro sizes shapes
• Look-ahead, macro clustering,obstacle evasion
• Floorist constraint-driven floorplan repair

red overlap
blue block- movement (no overlap)