ETS'05 Poster

1
An Efficient Test Set Embedding Scheme with
Reduced Test-Data Storage and Test Sequence
Length Requirements for Scan-based Testing
D. Kaseridis1, E. Kalligeros1, X.
Kavousianos2 D. Nikolos1
2Dept. of Computer Science University of
Ioannina, 45110, Ioannina, Greece
1Dept. of Computer Engineering
Informatics University of Patras, 26500, Patras,
Greece
e-mails kaserid_at_ceid.upatras.gr,
kalliger_at_ceid.upatras.gr, kabousia_at_cs.uoi.gr,
nikolosd_at_cti.gr
I. Test set Embedding
Core-oriented way of designing contemporary SoCs
leads to larger and denser circuits that require
greater test data volumes and longer
test-application times
The introduction of new, embedded testing
solutions that overcome these problems is of
great importance.
Test set embedding techniques that combine both
reduced hardware and test-data storage
requirements with short test sequences are
desirable
II. Seed Selection Algorithm
Table1. Seed-selection algorithm's criteria

• We consider the classical LFSR-based reseeding
  scheme LFSR, Bit and Vector Counter
• The algorithm receives as input the size L of
  the window (number of test-vectors) that each
  seed expands to and a set of test cubes T
• For determining a new seed the seed-algorithm
  makes uses of the well-known
• concept of solving systems of linear equations
  (i.e. assuming Gauss-Jordan elimination)
• The algorithm examines all possible linear
  systems and chooses one to solve

Criterion Description
1st Select the solvable systems that corresponds to the test cubes containing the maximum number of defined bits
2nd If there are more than one solvable systems selected by the 1st criterion, choose the solvable system that its solution leads to the replacement of the fewest variables ai in the L-vector window
3rd If there are more than one solvable systems selected by the 2nd criterion, select the solvable system that is nearest to the first vector of the window
Since at each step of algorithm, linear systems
corresponding to more than one test cubes will be
solvable at more than one positions of the
window, a set of heuristics is used (Table 1) for
selecting the system that will be actually solved
III. Test-sequence reduction scheme

• Rearrangement technique
• Main idea
• Order the seeds according to the number of
  useful segments
• If these volumes for every two successive
  windows differs at most by one ? Only a single
  extra bit per seed is needed for indicating this
  relation.
• Extra bit0 ? Same number of useful segment
• Extra bit1 ? One segment difference

• Seed-selection algorithm assumes a window of L
  successive test vectors for each selected seed.
  (Fig. 1)
• If the last vector of a window is not a useful
  one then all vectors from the last useful one to
  the last vector of each window are redundant

Example of rearrangement technique
Fig. 1. A window of L stages

• Proposed window segmentation approach
• Each window is segmented into a number (m) of
  equal-sized groups of test
• vectors (Fig. 2)
• The useful vectors of the window are included in
  the first k segments and thus the remaining m-k
  segments contain redundant test vectors and can
  be dropped during test generation

• Load Counter Down counter that maintains the
  necessary number of
• segments for each window
• Bit Counter controls the scan-in operation of
  each vector's bits
• Segment-Vectors Counter controls the generation
  of the test vectors of
• a single segment
• Segment Counter counts for the required number
  of segments for each
• window and is initialized for each seed with the
  value of Load Counter

Fig. 3. The proposed test-sequence reduction
scheme
Fig. 2. The proposed window segmentation technique
IV. Comparisons

• The proposed approach compares favorably against
  the most recent and efficient test set embedding
  technique in the literature (Reconfigurable
  Interconnection NetworksTCAD04)
• The comparison shows that the proposed scheme
  requires substantially smaller test sequences
  (Fig. 4) and hardware overhead (Fig. 5) for both
  32 (?) and 64 (?) scan chains

Fig. 4. Test sequence length reductions
Fig. 5. Hardware overhead reductions