Design of a

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Design of a Single Event Effect Mitigation
Technique for Reconfigurable Architectures
SAJID BALOCH
Prof. Dr. T. Arslan1,2 Dr.Adrian
Stoica3
Supervisory Team
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ACRONYMES

• SEU (Single Event Effect)
• SET (Single Event Transient)
• SEB (Single Event Burnout)
• SEL (Single Event Latch-up)
• Cfg (Configuration)
• EDAC (Error Detection and Correction)
• SoC (System on Chip)
• FPGA (Field Programmable Gate Array)
• DEU (Double Event Upset)
• TEU (Triple Event Upset )
• MEU (Multiple Event Upsets)

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RECONFIGURABLE ARCHITECTURES
a) FPGAs - SRAM -
Anti Fuse - EPROM b)
Reconfigurable SoC - General
purpose - Domain Specific

Re-Configurable SoC Architecture
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RADIATION EFFECTS RE-CONFIGURABLE ARCHITECTURES

• PERMANANT FAULTS (due to SEL, SEB etc)
• TEMPORARY FAULTS (due to SEU etc)

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SEU MITIGATION TECHNIQUES

• a) HARDWARE REDUNDANCY
• - Dual Modular Redundancy (DMR)
• - Triple Modular Redundancy
  (TMR)
• - EDAC Codes
• - Process Technology
• b) TIME REDUNDANCY
• c) COMBINATION (Hardware Time)

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Radiation Hardening SEU EFFECTS

• TRANSIENT FAULTS (Data Memory etc)
• PERMANANT FAULTS (Cfg. Memory)

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SEU EFECTS Synchronous Circuits
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SEU EFECTS Configuration Memory
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SEU EFECTS ROUTING OF A SIGNAL
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Proposed SEU/SET MitigationTechnique

• based on
• Temporal Data Sampling
• Weighted Voting
• Salient Features of The Proposed Technique
• Auto Correction Mechanism for
• 100 SEU Recovery
• 100 Double Fault Recovery
• Voter Faults Recovery

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Temporal Sampling
Primary Section
Secondary Section
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TEMPORAL SAMPLING Clock Scheme

• 3 derivates of Main Clock
• Each Clock is Phase shifted
• 25 duty Cycle

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Minimized TermX4.X3.X0 X5.X3.X0 X5.X4.X0
X4.X3.X1 X5.X3.X1 X5.X4.X1 X4.X3.X2
X5.X3.X2 X5.X4.X2 X5.X4.X3 X3.X2.X1.X0
X4.X2.X1.X0 X5.X2.X1.X0
Weighted Voter Circuit
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SEU in Secondary Section
Case Example
Node Before SEU After SEU Voting Weights 1 0 Voting Weights 1 0 Total Votes 1 0 Total Votes 1 0
1 1 1 2 - 8 1
3 1 1 2 - 8 1
5 1 1 2 - 8 1
2 1 0 - 1 8 1
4 1 1 1 - 8 1
6 1 1 1 - 8 1
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Multiple Bit Upset
Case Example
Node Before SEU After SEU Voting Weights 1 0 Voting Weights 1 0 Total Votes 1 0 Total Votes 1 0
1 1 1 2 - 5 4
3 1 0 - 2 5 4
5 1 0 - 2 5 4
2 1 0 1 - 5 4
4 1 1 1 - 5 4
6 1 1 1 - 5 4
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Hardware Implementation of Proposed
Scheme with Auto-Correction Mechanism
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Single Event Transition FaultData / Clock
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SEU/SET Simulator

• SEUs can be injected at instance
• SEU of any duration can be injected
• Multiple upsets can be injected

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Performance AnalysisFault Coverage
 Mitigation Scheme age Fault Tolerance age Fault Tolerance age Fault Tolerance age Fault Tolerance
SET SEU DEU TEU
Proposed Scheme 100 100 100 50
F. Lima etal Scheme 63 100 - -
D. Mavis etal Scheme 100 100 32 18
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Performance AnalysisArea Overhead
Results are based on 0.13µm CMOS technology