Time-Domain Equivalent Design of Continuous-Time SD Modulators

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Head of the group Prof. Franco Maloberti
University of Pavia Department of Electronics Via
Ferrata, n1, 27100 Pavia
17th IEEE International Conference on
Electronics, Circuits and Systems
Time-Domain Equivalent Design of
Continuous-Time SD Modulators
PhD Student Oscar Belotti email
oscar.belotti_at_unipv.it sito http//ims.unipv.it
/oscar/
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University of Pavia
OUTLINE
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Introduction
Limitations of conventional methods
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New design methodology
Design procedure for a Third Order CT SD
Design at transistor level
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DESIGN PROCEDURE
Equivalent CT architecture
DT prototype
DT/CT transformation
First Step
Final step
Discrete time
Continuous Time
Design task
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Design task
Mathematical approach
Modified Z Transform
No accurately model for the effect of loop delay

State-Space Method
Uncommon in circuit design
Impulse Invariant Transformation
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General DT prototype Conventional Third Order
Low-pass modulator.
Loop Transfer Function
The expanded view of the same topology
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Impulse invariant transformation
Final architecture
Drawback of this Method ! ! !
It enables superposition only if DAC impulse
response are the same.
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Proposed Solution
Chain of three integrators
where
Therefore it is necessary to use
Equivalence conditions
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Proposed Solution
Chain of two integrators
Therefore it is necessary to use
Equivalence conditions
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Proposed Solution
Single Integrator
Final CT architecture


The CT coefficients depend on integrals of time
responses of the DACs
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Design Benefit
The CT equivalent design need the estimation of
single and multiple integrals of DAC impulse
responses.
The integrals can be done with circuit simulators.
The nonidealities of building blocks give rise to
an error in the integration results that
automatically account for real limits in the
feedback coefficient.
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Design Example
Starting DT prototype Conventional Low-pass
Third order DT modulator with all feedback
coefficients equal to one.
CT feedback DACs impulse responses
The responses have the same area
Normalized time response (t/T)
The shape of the time responses are relevant for
obtaining the exact equivalence
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Simulation Result
Output spectrum
Time domain simulation
Normalized time response (t/T)
The values at tT are the coefficients needed
for the CT design.
Input Signal Frequency (Fin) 14.29 MHz _at_
-4dBFs Oversampling Ratio (OSR) 16 _at_ 2048
Samples
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CONCLUSION
This design procedure
Permits to optimize the design of a CT SD
Modulator
Operates in time domain and could be directly
used with transistor level simulators.
Compensate the effect due to nonidealities of the
blocks
Improves the computer aided design technique.
Allow to use different types of DACs
Optimize overall performance.
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The End
Thank you for your attention
Athens, Greece ICECS 2010 12 -15
December 2010