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Advanced Semiconductor Substrates

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Advanced Semiconductor Substrates by Heterogeneous Integration Nathan Cheung Dept of EECS, UC-Berkeley cheung_at_eecs.berkeley.edu SOI SSOI GeOI – PowerPoint PPT presentation

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Title: Advanced Semiconductor Substrates


1
Advanced Semiconductor Substrates by
Heterogeneous Integration Nathan Cheung Dept of
EECS, UC-Berkeley cheung_at_eecs.berkeley.edu
SOI
SSOI
GeOI
2
OUTLINE
  • Motivations for SOI, SSOI, and SiGeOI substrates
  • Layer Transfer Technologies
  • - Bonding
  • - Delamination
  • - Surface Smoothing
  • Challenges and Equipment Opportunities
  • Application of layer transfer for microsystem
    integration

3
(No Transcript)
4
Why Strain Si ?
Compound Semiconductor, September 2002
5
Why GeOI ?
  • Higher carrier mobility than that of silicon
  • Expected to be compatible with high-k dielectric
  • Dopant activation temperatures are much lower,
    easier to form ultra-shallow junctions.

6
Cost of Silicon Real Estate
200mm Epi wafer
1812 sq/ft House Menlo Park, CA
200mm SOI or s-Si wafer
944,492
80
200-400
0.56 /cm2
0.25/cm2
0.44-0.88/cm2
7
Principle of Layer Transfer
Defining a Zipper Layer underneath donor wafer
surface
Bond handle/donor wafer pair with bonding energy
larger than unzipping surface energy
Transferred layer
Initiate unzipping
Can be recycled
8
Advantages of Layer Transfer Approach
  • Donor wafer can be recycled
  • Transferred thickness and buried oxide thickness
  • are independently controlled
  • Lower processing temperature than SIMOX approach
  • Multi-stack structures can be achieved
  • Silicon-on-Anything (SOA) composite substrates

9
Direct Wafer Bonding
Chemical Cleaning HF, H2SO4, H2O2
IR Transmission Image Through a Bonded Pair
Plasma exposure
Room temperature bonding
Complete bonding over 4 inch diameter
Annealing
10
Delamination Methods
(1) Exfoliation of implanted hydrogen SOITEC,
Amberwave
(2) Cleavage along implant damage region (gas
jet) Sigen
(3) Mechanical rupture of Porous Si (water jet)
Canon
11
Source www.soitec.com
12
Requirements for Direct Bonding
  • Surface micro-roughness nm
  • No macroscopic wafer warpage
  • Minimal particle density and size
  • - 1um particle will give 1000um void
  • Contamination free surface

13
Inter-surface Forces
Weak
Van der Waals lt 20 mJ/m2
H-bonding lt 500 mJ/m2
Covalent bonding gt 2000 mJ/m2
Strong
14
Hydrophilic Bonding Model
O
O
Si
Si
O
O
H
H
H2O
H2O
H
H
O
O
Si
Si
O
O
Si-OH Si-OH ---gt Si-O-Si H2O Si 2 H2O ---gt
SiO2 2 H2
Room temp bonding
lt 100 oC
gt 100 oC
15
Gap Closing Criteria
1) For R lt 2t
2) For R gt 2t
lt
E Youngs modulus
Tong et al, Thickness Considerations in Direct
Silicon Wafer Bonding, JECS, Vol. 142, No.11,
pp. 3975-3979, 1995
16
Criteria for Gap Closing Surface Energy Dependence
g 10mJ/m2
Wafer thickness 0.5 mm
g 100mJ/m2
R gt2t
Gap closing
R lt 2t
Gap opening
Q.-Y. Tong and U.M. Gösele, Adv. Mater., Vol. 11
(1999)
17
What is the maximum particle size allowed to
ensure gap closing ?
For R large compared with wafer thickness t,
condition for gap closing is independent of t and
is given by h lt 2.6 (R
? /E)1/2 ? bonding energy 10-5 J/cm2 (very
conservative value) E Si Youngs modulus (
1.66 x 10-5 J/cm for (100) Si ) R 1cm (
particles are 2 cm apart) h max 0.2 um

18
CMP is required to reduce deposited film
roughness !
After CMP RMS roughness 0.93nm BONDABLE
Deposited Poly RMS roughness 10.2nm NOT
BONDABLE
Epi SiGe as grown
Epi SiGe after CMP
19
Plasma activated surface model
PLASMA
Surface damage 1-2 nm
High coverage of OH
Si rich surface
High mobility of H2O
Defect layer
20
Bonding Energy vs. Temperature
Si (100) Fracture Strength
Cho et al, UCB, 2000.
21
The Smart-Cut? Process (SOITEC)
Bruel, Mat. Res. Innov.,1999
22
Exfoliation Cut depth close to implant damge peak
Hochbauer, MRS 2000
23
The NanocleaveTM Process (SiGen)
DONOR RECLAIM / SURFACE FINISH
DONOR
OXIDIZE AND CLEAVE PLANE FORMATION
BOND
EPI-Smooth/Thicken
rT-CCP
NEW HANDLE
  • Key Process Steps
  • Epitaxial deposition
  • Implantation
  • Oxidation
  • Plasma activation and bonding
  • Layer transfer and cleaving
  • Epitaxial smoothing and thickening

Malik et al, Semicon Europa, 2003
24

Cold-Cut Edge Initiated Mechanical Cleavage
Stress Concentration at Crack Tips
Length of the crack 2a Radius of curvature at
tip ? Applied Stress ? Stress at crack-tip
?C
25
Example Calculation Estimate the stress
enhancement factor at crack tip for mechanical
separation
With a 0.1 to 1 cm and ? 0.1-1nm, Enhancemen
t factor 2000 - 20000
Lattice fringe image of the tip of a 111
cleavage crack in Silicon
Note 146 psi pressure (106 N/m2) applied within
the crack will be enhanced to 1010 N/m2 at the
crack tip which is roughly the yield stress of
most brittle materials
26
Hydrogen Induced Thermal Separation rms 8.5 nm
NanoCleave? rms 0.8nm
Current et al, European Semiconductor, Feb 2000
27
Ultra-Thin (lt1KÅ tSOI) Non-Uniformity
28
The ELTRANTM Process (Canon)
Sakaguchi et al, IEEE SOI Conf. , 1999
29
Surface Smoothing by Hydrogen anneal
As-split surface
After-anneal surface
30
Key requirements Good uniformity Low Surface
Roughness
UT-SOI Range Capability
Source IEEE 2002 SOI Conference
31
s-Si/SiGe on Insulator Process (IBM)
Huang et al. 2002 Trans. Elec. Dev. 49(9) 1566.
32
G. Cellar, SOITEC Technical Notes, 2003
33
Relaxed SiGe surface roughness can be reduced
Malik et al, Semicon Europa,2003
34
FLCC Research Uniformity and Roughness Control
  • Low-temperature plasma surface treatment to
    improve
  • bonding strength between SiO2 and SiGe
  • Other ways to enhance bonding strength (photons,
    ions, vapor)
  • Modeling and verification of thermal, implant,
    and bonding stress
  • effects on transferred thickness and roughness

35
Plasma Assisted Bonding for SGOI
EXP. Set-up
Si-Ge bonding strength
Refractive Infrared Imaging
Image Si-Ge pair
36
Low temperature process for ?bond gt ?cut
Temperature (C)
gSi(100)
gcut
gSi(110)
g (J/m2)
gbond
gcut gt gbond
gcut lt gbond
1 cm
Transferred Si
Cho and Cheung, APL, 2003
Partial transfer
No transfer
Full transfer
37
7E16
Dose Dependence of blister depths
40keV H 600oC anneal
5E16
7E16
1E17
Hochbauer et al ,JAP, 2000
38
Manufacturing Equipment Opportunities
  • High-throughput, low-cost Epi Reactors
  • CMP of SiGe and Strained Si
  • High Current Hydrogen implanters
  • Plasma Activated Bonders
  • Mechanical Delamination Machines

H Plasma Implanter
Plasma Bonder
Gas Jet Delamination
39
Zero-footprint optical metrology wafer
Data transmission/ diagnostics
Dielectric layer
MEMS Sensor
Si
Detector
Photon emitter
Photon emitter
Data processing, storage unit
Li-polymer Battery
  • Self-powered diagnostic and monitoring wafer
  • Deposition/etching uniformity and CMP end-point
    mapping.
  • Work in hostile processing environments ( Plasma,
    wet etching, CMP).
  • 1 thickness resolution is achievable.

www.sfr.berkeley.edu
40
Heterogeneous Integration of GaN LED, CdSe
optical filter ,Si detector, and microfluidic
channels
Light sources Blue (463nm) and green (525nm)
(In,Ga)N LEDs were used to excite yellow-green
(494/518) and red-orange (565/580) FluoSpheres
carboxylate-modified microspheres ( 0.04 µm in
size), respectively. Filters CdS (1.1 ?m) and
CdS0.9Se0.1 (1.1 ?m) filter were used to filter
out the emission light for blue and green LEDs,
respectively. Fluidic channel PDMS
(polydimenthyl siloxane) channel 2mm wide, 100?m
deep and 7mm long.
Packaged prototype XYZ chip.
41
Wafer Bonding Application Polymer Battery,
switch, and LED Encapsulation
Both Top Bottom
Bottom Wafer
Photo Switch
Battery
LED
Top Wafer
42
Summary
  • SOI substrate is a relatively mature technology
    but ultra-thin SOI poses new challenges to meet
    stringent uniformity and roughness specifications
  • SSOI and GSOI substrates offer combined
    advantages of SOI and high mobility channels.
  • Layer transfer recipes have to be tailored to
    ensure uniformity and thermal stability of SSOI
    and GSOI structures
  • Challenges for process control , metrology, and
    manufacturability
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