Fabrication of semiconductor GEMs

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Fabrication of semiconductor GEMs

• or
• Why GEMs are still made from kapton

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Overview

• Historical info on GEMs
• What, how etc.
• Development of current devices
• New developments in GEM technology
• i.e. what Ive been doing for 2 years

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What is a GEM?
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GEMs are

• Gaseous

A type of micro-pattern gas detector which has
been developed for use in applications requiring
high gain, high speed and low noise measurement

• Electron

• Multipliers

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History of GEMs

• First demonstrated by F. Sauli (NIM A 386 ( 1997)
  53 l-534)
• The GEM foil consists of two metal electrodes
  separated by an insulating film (kapton,
  polyimide, PCB)

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History of GEMs
Schematics of first test GEM structure. GEM
placed inside an MWPC to replace one of the
cathodes

• F. Sauli (NIM A 386 ( 1997) 53 l-534)

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History of GEMs
GEMs are used to amplify charge created by
incident radiation utilising the avalanche
effect.
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History of GEMs
GEM foil
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History of GEMs
Close up of GEM field line distribution
L. Shekhtman NIM A 494 (2002) 128141
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History of GEMs
Theory of avalanche gain in gas detectors
The total multiplication or gas gain from an
electron travelling from cathode to anode is
given by
Where a is the Townsend constant, integrated over
the transit distance from cathode to anode
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History of GEMs
Theory of avalanche gain in gas detectors
The Townsend constant is related to the low
current, corona discharge region of an ionising
gas
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History of GEMs
Theory of avalanche gain in gas detectors
Assuming a kinetic model were W is the minimum
ionisation energy we get
(1)
Were l is the mean free path and E is the
electric field
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History of GEMs
Theory of avalanche gain in gas detectors
Taking s as the cross section for ionisation
between electrons and gas atoms gives were NL
is Loschmidts number given by NA Avogadros
number, R the gas constant, P/T ambient pressure/
temp
(2)
(3)
P/T can be expressed as the ratio
(4)
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History of GEMs
Theory of avalanche gain in gas detectors
Combining these we get
(6)
Defining we can re-write (6) as
(6a)
Were W and lq are physical parameters of the gas
it is easy to see that the gain depends on E and
q
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History of GEMs

• F. Sauli (NIM A 386 ( 1997) 53 l-534)

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Development of GEM foils
Gain of single GEM foil in Ar-CO2 atmosphere at
atmospheric pressure
(J. Benlloch et al. NIM A 419 (1998) 410-417)
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Development of GEM foils
Variation in time response of gain for different
hole profiles
(J. Benlloch et al. NIM A 419 (1998) 410-417)
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Development of GEM foils
Use of GEM foils for neutron detection using a PP
converter
V. Dangendorf et al. NIM A 535 (2004) 9397
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Development of GEM foils
Images taken using GEM based neutron imaging
system using a position sensitive readout system
V. Dangendorf et al. NIM A 535 (2004) 9397
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Development of GEM foils
Schematic of multi-GEM system utilising different
photocathodes, readout is by microstrip detector
D. M.ormann et al. NIM A 504 (2003) 9398
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Development of GEM foils
Time response from semi-transparent cathode
multi-GEM system detecting UV photons
D. M.ormann et al. NIM A 504 (2003) 9398
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Development of GEM foils
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Development of GEM foils

• Other areas for experimentation and development
  include
• Low pressure GEM operation
• R. Chechik et al. NIM A 419 (1998) 423-428
• Cryogenic GEM operation
• A. Bondar et al. NIM A 524 (2004) 130141

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GEM applications

• Atmospheric pressure and above, GEMs can be used
  as an amplifier stage for detection of lightly
  interacting particles i.e. MIPS.
• No further amplification is required in this case
• Neutron detector with converter.
• Low pressure detectors with CsI photocathode for
  ultra soft x-rays and UV photons in single
  electron counting operation
• RICH detectors

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Semiconductor GEMs
Fabrication of GEM foils from rigid semiconductor
or insulating substrates is desirable for a
number of reasons

• Removes effect of sagging as device is powered up
• Use of reactive gas mixtures could be explored
• Higher possible baking temperature (improved
  sealing of vacuum chambers)
• Greater density of holes possible due to existing
  advanced lithography and processing technology

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Semiconductor GEMs
Very small features and pitches produced in Si
using dry etch technology
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Semiconductor GEMs
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Semiconductor GEMsDesign for test device
Test structure with 4 different hole diameters 80
200 mm
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Semiconductor GEMsDesign for test device
Single test pattern
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Semiconductor GEMsMetallisation
The device structure as shown here is a metallic
layer with an insulating material separating
them. This implies we need to passivate the Si
surface and then apply a metallic film.
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Semiconductor GEMsMetallisation
Preliminary attempts used a PECVD (plasma
enhanced chemical vapour deposition) layer of
SiO2 with 200 nm of Au as the metallisation.
The problem is gold doesnt stick very well.
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Semiconductor GEMsMetallisation
Metallisation recipe changed to include Ti
adhesion layer, this successfully survives
several future processing steps.
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Semiconductor GEMsEtching passivation layer
Schematic of reactive ion etching (RIE) plasma
reactor
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Semiconductor GEMsEtching passivation layer
The theory of the RF plasma operating in glow
discharge regime starting from the force
exerted on a single electron then taking the x
component of the motion and substituting the
sinusoidal electric field it is possible to
define the power absorbed by the gas
nc neutral collision frequency E electric
field
ne number density of electrons w E field
frequency melectron mass Eo max field strength

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Semiconductor GEMsEtching passivation layer,
problems
None. This is the only step that never had any
problems
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Semiconductor GEMsEtching Si
Schematic of inductively coupled plasma (ICP)
reactor
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Semiconductor GEMsEtching Si
The ICP upper chamber this is what creates the
denser plasma responsible for the faster etching
rate. The frequency is fixed at 13.65 MHz the
power can be varied depending on the attached
power supply.
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Semiconductor GEMsEtching Si

• Parameters for ICP etching
• Coil power Determines the density of the plasma
  in the upper chamber
• Platen power determines the potential difference
  accelerating ions towards the surface
• Pressure has an effect on the transfer of ionic
  species into and out of the etched features

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Semiconductor GEMsEtching Si
SF6/ O2 mixture used for etching the initial
features. Preferentially etching vertically
Plasma chemistry switched to C4F8 This causes a
build up of polymer over all surfaces
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Semiconductor GEMsEtching Si
Switching the plasma gasses back to SF6/O2 starts
etching again
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Semiconductor GEMsEtching Si, problems 1

• ICP (inductively coupled plasma) etching of Si is
  very sensitive parameter sensitive.
• Incorrect choice of any of the parameters can
  lead to non-successful etch.
• Recipe design is a fairly time and material
  intensive process

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Semiconductor GEMsEtching Si, problems 1
Wrong pressure causes feature to close up towards
the bottom. This stops etching after a given
depth.
low pressure high pressure
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Semiconductor GEMsEtching Si, problems 1
Varying the platen power modifies the profile of
the hole.
low platen power high platen power
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Semiconductor GEMsEtching Si, problems 1
Excess passivation build up caused by poor cycle
time selection
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Semiconductor GEMsEtching Si, problems 1

• But, why are these all serious fatal flaws
• With poor parameter choice, and subsequent poor
  etch profile the depth, diameter and actual shape
  of the etched features is pretty vague

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Semiconductor GEMsEtching Si, problems 1
These images are of the two ends of the same
hole. Obviously there is a problem, they arent
circular and theyre different sizes
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Semiconductor GEMsEtching Si, problems 1
Improved shape, high mask erosion is causing
damage to metal surface
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Semiconductor GEMsEtching Si, problems 1
Circular holes ,reduced mask erosion but still
causing damage to metal surface
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Semiconductor GEMsEtching Si, problems 1
Round holes. No surface damage
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Semiconductor GEMsEtching Si, problems 1
The parameters for the successful etch are as
follows Coil    900W (etch) / 800W (dep)
Platen    13W (etch) / 0W (dep) Etch   
SF6/O2 130 / 13 sccm Deposition    C4F8 110
sccm Switch    11s (etch) / 7s (dep) Pressure
30 mtorr   This process produces an etch rate
of 3- 3.5 mm/min
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Semiconductor GEMsEtching Si, problems 1
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Semiconductor GEMsEtching Si, problems 2

• ICP switched process etch does not etch SiO2
• Need to align from the other side to be able to
  etch both SiO2 layers

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Semiconductor GEMsEtching Si, problems 2
First attempt at aligning front to back a
complete and utter mismatch
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Semiconductor GEMsEtching Si, problems 2
Kaleidoscope effect from partial rotational
mismatch
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Semiconductor GEMsEtching Si, problems 2
Fully etched device holes circular and properly
aligned. Looks suitable for testing
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Semiconductor GEMsEtching Si, problems 2
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Semiconductor GEMsTesting devices
Constant current 1mA over large voltage range
need to get lower current, implying better field
characteristics
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Semiconductor GEMsTesting devices

• What to do? Change oxide layer, PECVD oxide has
  lower resistivity and break down field than
  thermal oxide.
• Other problems relating to integrity of the layer

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Semiconductor GEMsTesting devices
Very low current lt5 pA over large range looks
very promising
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Semiconductor GEMsTesting devices
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Semiconductor GEMsTesting devices
Measurements of changing current as a b source is
applied and removed from the sample.
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Semiconductor GEMsTesting devices
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Semiconductor GEMsTesting devices
Until this was discovered
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Semiconductor GEMsWhat next?

• Tests showed short between the metal layers and
  the Si.
• Ti diffusion causing conductive TixOy at hole
  edge
• Solution. Change metal again. Use Pd, very low
  diffusion in SiO2, sticky unlikely to come off.
• Other angle looking at only using one SiO2 layer
  to cut down the possibilities of shorts developing

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Semiconductor GEMsWhat next?

• Use Quartz substrate, this has one really big
  advantage,
• No need for separate passivation
• This also removes the likelihood of shorts
• Sounds perfect
• Problem, cannot get dry etching facilities for
  deep etching in quartz and wet etching is too
  isotropic for very deep etching

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Semiconductor GEMsRecent developments

• Unfortunately not many.
• The STS ICP has been down since June.
• Came back on line last week, making 12 months of
  down time in the last 26.
• Samples are being etched now with Pd
  metallisation.
• Masks designed for etching of quartz substrate

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Semiconductor GEMsFuture developments

• Adding additional Si3N4 to SiO2 surface to reduce
  possibility of interface effects
• The next few weeks will produce more completed
  devices for testing

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ICP theory