Bottlenecks of SIMD

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Bottlenecks of SIMD

• Haibin Wang
• Wei tong

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Paper

• Bottlenecks in Multimedia Processing with SIMD
  Style
• Extensions and Architectural Enhancements One
• IEEE TRANSACTIONS ON COMPUTERS, VOL. 52, NO. 8,
  AUGUST 2003

• Deepu Talla, Member, IEEE ,Lizy Kurian John,
  Senior Member, IEEE, and Doug Burger, Member, IEEE

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Outline

• Introduction
• Bottlenecks Analysis
• MediaBreeze Architecture
• Summary

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Introduction

• It is popular to use multimedia SIMD extensions
  to speed up media processing, but the efficiency
  is not very high.
• 75 to 85 percent of the dynamic instructions in
  the processor instruction stream are supporting
  instructions.

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Introduction

• The bottlenecks are caused by the loop structure
  and the access patterns of the media program.
• So instead of exploiting more data-level
  parallelism, the paper focuses on improving the
  efficiency of the instructions supporting the
  core computation.

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Introduction

• This paper has two major contributions
• Firstly, it focuses on the supporting
  instructions to enhance the performance of SIMD
  which is an innovation.
• Secondly, it gives a method to reduce and
  eliminate supporting instructions with the
  MediaBreeze architecture.

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Nested Loop
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The analysis of loop architecture

• The sub-block is very small which leads to the
  limited DLP because it needs many supporting
  instructions.
• There are 5 loops for every block which waste so
  much time on braches.
• You need to reorganize the data to use SIMD

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Access patterns
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Access patterns

• The addressing sequences are complex and big part
  which need lots of supporting instructions to
  generate them.
• Using general-purpose instruction sets to
  generate multiple addressing sequences is not
  very efficient.

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The overhead instructions

• Address generation address calculation
• Address transformation data movement, data
  reorganization
• Loads and Stores memory
• Branches control transfer, for-loop

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Architecture
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Instruction Structure
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Breeze Instruction Mapping of 1D-DCT
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Full Map

• . five branches,
• . three loads and one store,
• . four address value generation (one on each
  stream
• with each address generation representing
  multiple
• RISC instructions),
• . one SIMD operation (2-way to 16-way parallelism
• depending on each data element size),
• . one accumulation of SIMD result and one SIMD
• reduction operation,
• four SIMD data reorganization (pack/unpack,
  permute,
• etc.) operations, and
• . shifting and saturation of SIMD results.

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Performance Evaluation

• cfa,dct, motest,scale
• G711, decrypt
• Aud, jpeg, ijpeg

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Any improvement?

• Why not higher efficiency in cfa?
• Memory latency!
• Solution?
• Prefetch!

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Evaluation

• Advantage
• Eliminating and reducing overhead.
• Much better than normal SIMD extension.
• 0.3 processor area, less 1 total power
  consumption.
• Drawback
• Complicated instruction.
• Who will design a compiler for this?