Multiprocessor Systems

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Multiprocessor Systems

• A presentation by
• Chris Hargreaves

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Flynns Classification

• SISD Single instruction single data
• SIMD Single instruction multiple data
• MISD Multiple instruction single data
• MIMD Multiple instruction multiple data

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Bisection Bandwidth

• Split the system into a half (or next to half)
  and find the bottleneck.

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System Topologies

• The pattern of connections between the processors

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Shared Bus

• Processors communicate over a shared bus
• Most cases the processors communicate directly
  with their locally memory
• More processors cause delays as traffic increases

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Ring

• Direct connections between processors
• Allows simultaneous links to be active
• Data may have to travel through multiple
  processors before reaching its final destination

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Shared Bus Ring
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Tree Topology

• Each processor has three connections
• Lowers the diameter
• Only one unique path between any pair of
  processors

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Mesh Topology

• Each processor connects to the its left and
  right, top and bottom
• Without wraparound connections has a diameter of
  2 n(1/2). With it has n(1/2)

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Tree Mesh
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Hypercube Topology

• Each processor connects to all other processors
  whose binary value differs by only one bit
• Ex Processor 0 connects to 1, 2, 4 and 8
• Low Diameter (lg n). Good.

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Completely Connected

• Each processor has (n-1) connections
• Diameter is a constant 1

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Hypercube Completely Connected
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MIMD Architecture

• Refers to connections with respect to system
  memory

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SMP (Symmetric Multiprocessor)

• UMA Uniform Memory Access
• NUMA - Nonuniform Memory Access
• CC-NUMA Cache Coherent NUMA
• COMA Cache Only Memory Access
• NOW COW - Multicomputer

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UMA

• Equal access to all locations in shared memory
• Each processor may also have its own cache memory
• Interact with memory over a communication
  mechanism such as a shared bus

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UMA
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NUMA

• Can access the memory closest
• Non Uniform access times to memory

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NUMA
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CC-NUMA

• Same as NUMA except each processor includes cache
  memory
• Problem occurs when two caches hold the same
  piece of data
• Must have coherence to make sure caches contain
  the same information

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COMA

• Solution to CC-NUMA
• Local Memory treated as cache
• If data is loaded multiple times, one is marked
  as the Master Copy which is kept current
• Few of these machines have every been built

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Multicomputing

• NOW Network of workstations
• COW Cluster of workstations
• SETI_at_Home
• United Devices (www.ud.com)

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MMP

• Massively Parallel Processor
• Process massive ammounts of data in parallel
• Typically at the level of the ALU
• Communicate using shared memory
• Example IBM Blue Gene Computer