Introduction to Computer Architecture

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Introduction to Computer Architecture and
Design Ji Chen Section T TH 100PM 230PM

Prerequisites ECE 4436
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Instructor Ji Chen Email
jchen18_at_uh.edu Tel [phone] Office
W328 Office Hour T TH 230-330 or by
appointment TA None
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(No Transcript)
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Course Contents

1. Introduction, basic computer organization
2. Instruction formats, instruction sets and their
   design
3. ALU design Adders, subtracters, logic operations
   
4. Multiplication, division, floating point
   arithmetic
5. Datapath design
6. Control design Hardwired control,
   microprogrammed control
7. Pipelining
8. Memory systems
9. I/O

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Web http//www.egr.uh.edu/courses/ece/ECE5367/
HW/Quiz/Lab 10
Project 15
Exam 1 25
Exam 2 25
Exam 3 25
Grading
Academic Honesty Statement
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Computer Organization and Design The
Hardware/Software Interface by David A.
Patterson, John L. Hennessy, 3rd edition
Required NOT REQUIRED
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Home works/quiz  There will be several graded
homework/lab assignments. Home works turned in
late will be accepted only under
extraordinary circumstances. Labs  Laboratory
assignments may be worked in teams of two (2)
however, there should be no collaboration between
teams . .  Lab assignments turned in late will
be penalized 25 points for each calendar day. 
Both students in a team will receive the same
grade for the project. Projects Teams of four
(4) describe computer architecture of a modern
technology Exams  two mid-term exams,
and one final exam.  A missed exam will result
in a grade of zero ? Let me know immediately if
you have any situation Final Exam -
TBD Grading  Your final grade will be computed
as follows  
HW/Quiz/Lab 10
Project 15
Exam 1 25
Exam 2 25
Exam 3 25
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• Since 1946 all computers have had 5 components

Processor
Input
Memory
Output
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• TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20

MBus Module
SuperSPARC
Floating-point Unit
L2
CC
Integer Unit
MBus
DRAM Controller
MBus control M-S Adapter
L64852
Inst Cache
Ref MMU
Data Cache
STDIO
SBus
serial
kbd
SCSI
Store Buffer
SBus DMA
mouse
Ethernet
audio
RTC
Bus Interface
SBus Cards
Floppy
Message Bus (Mbus)
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Computer Architecture
Application
Operating
System
Compiler
Firmware
Instruction Set Architecture
I/O system
Instr. Set Proc.
Datapath Control
Digital Design
Circuit Design
Layout

• Coordination of many levels of abstraction
• Under a rapidly changing set of forces
• Design, Measurement, and Evaluation

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Forces on Computer Architecture
Technology
Programming
Languages
Applications
Cleverness
Computer Architecture
Operating
Systems
History
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Mixed-Signal
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Where are We Going??
ECE 5367 Spring 08
?
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Performance

• Purchasing perspective
• Given a collection of machines, which has the
• Best performance ?
• Least cost ?
• Best performance / cost ?
• Design perspective
• Faced with design options, which has the
• Best performance improvement ?
• Least cost ?
• Best performance / cost ?
• Both require
• basis for comparison
• metric for evaluation
• Our goal understand cost performance
  implications of architectural
• choices

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Two Notions of Performance
Plane
Boeing 747
Concorde

• Which has higher performance?
• Time to do the task (Execution Time)
• execution time, response time, latency
• Tasks per day, hour, week, sec, ns. ..
  (Performance)
• throughput, bandwidth
• Response time and throughput often are in
  opposition

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Definitions

• Performance is in units of things-per-second
• bigger is better
• If we are primarily concerned with response time
• performance(x) 1
  execution_time(x)
• " X is n times faster than Y" means
• Performance(X)
• n ----------------------
• Performance(Y)

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Example

• Time of Concorde vs. Boeing 747?
• Concord is 1350 mph / 610 mph 2.2 times faster
• 6.5 hours / 3 hours
• Throughput of Concorde vs. Boeing 747 ?
• Concord is 178,200 pmph / 286,700 pmph 0.62
  times faster
• Boeing is 286,700 pmph / 178,200 pmph 1.60
  times faster
• Boeing is 1.6 times (60) faster in terms of
  throughput
• Concord is 2.2 times (120) faster in terms of
  flying time

We will focus primarily on execution time for a
single job Lots of instructions in a program gt
Instruction throughput important!
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CPU Seconds Instructions x Cycles x
Seconds Performance Program Program
Instruction Cycle
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Amdahl's Law
Speedup due to enhancement E
ExTime w/o E Performance w/
E Speedup(E) --------------------
---------------------
ExTime w/ E Performance w/o
E Suppose that enhancement E accelerates a
fraction F of the task by a factor S and the
remainder of the task is unaffected
then, ExTime(with E) ((1-F) F/S) x
ExTime(without E) Speedup(with E)
1
(1-F) F/S
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Base Machine Op Freq Cycles CPI(i)
Time ALU 50 1 .5 23 Load 20 5
1.0 45 Store 10 3 .3 14 Branch 20 2
.4 18 2.2
Typical Mix
How much faster would the machine be if a better
data cache reduced the average load time to 2
cycles? How does this compare with using branch
prediction to save a cycle off the branch
time? What if two ALU instructions could be
executed at once?