Performance Analysis of Two Synchronizers

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Performance Analysis of Two Synchronizers

• Zhen Zhang Jim Garside
• APT group, School of Computer Science
• University of Manchester

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Necessities for Data Synchronization

• Multi-Clock Domains in SoC Devices
• Difficulties in Single Clock Distribution
• Modules with Different Frequencies
• Dynamical Changing Clock Relationships
• GALS architecture

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Choice of Synchronizers

• Mutual Relationships of Clock Domains
• Most General Case Mutually Asynchronous
• Reliability and Performance of Synchronizers
• Metastability
• Latency and Throughput
• Systematic Analysis of Two-Flop Synchronizer
  Families

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Two-Flop Synchronizer
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Time Boundaries for Forward Cycle

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Plot of Time Boundaries
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Probability and Average Forward Cycle
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Average Forward Cycle
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Fast Four-Phase Synchronizer
Zero latency synchronizers using four and two
phase protocols, R.Dobkin and R.Ginosar,
Technical Report, Oct 2007
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Time Boundaries
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Plot of Forward and Backward Cycle Time
Boundaries
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Average Forward and Backward Cycles
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Conclusion

• Performance analyses of two recognized
  synchronizers are developed
• Analytical models for average data cycles provide
  designers with more accurate information for
  performance comparison purpose
• Non-linear behaviour of backward cycle indicates
  the dependencies on forward cycle
• Full analysis of two-phase synchronizer is
  conducted (not shown in this presentation)

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Future Work

• Analyze forward and backward cycle interactions
  for two-flop and four-phase synchronizers
• Expand the analysis of single word transfer to
  burst-mode transfer
• Incorporate effects of metastability and
  interconnection delays into our model
• Apply similar analysis to other synchronizers

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Questions