Title: Final Chapter Packet-Switching and Circuit Switching
1Final Chapter Packet-Switching and Circuit
Switching
- 7.3. Statistical Multiplexing and Packet
Switching - Datagrams and Virtual Circuits
- 4. 4 Time Division Multiplexing and Circuit
Switching
25.7.1 Statistical Multiplexing
- Multiplexing concentrates bursty traffic onto a
shared line - information flow should include source address
and destination address - Greater efficiency and lower cost
3Statistical Multiplexing -Asynchronous Time
Division Multiplexing
- Statistical Multiplexing involves the sharing of
transmission channels (resource) by several
connections A, B, , Z or information flows
which will be transmitted (served) on demand
(statistically). Thus Significant economies of
scale can be achieved - Ports A, B, , Z in the multiplexer should
provide sufficient number of buffers information
packets will be stored and forward, thus cause
delay - The shared channel would be E-carrier (T-carrier)
or SDH (SONET)
Shared Channel
Statistical Multiplexing
4Multiplexer/Demultiplexer inherent in Packet
Switches
Multiplexer
DeMultiplexer
- Packets/frames forwarded to buffer prior to
transmission from switch - Multiplexing occurs in these buffers
5Multiplexer Modeling
- Arrivals What is the packet interarrival
pattern? - Service Time How long are the packets?
- Service Discipline What is order of
transmission? - Buffer Discipline If buffer is full, which
packet is dropped? - Performance Measures Delay Distribution Packet
Loss Probability Line Utilization
6Chapter 7Packet-Switching Networks
- 7.3 Datagrams and Virtual Circuits
7The Packet Switching Function
- Store and then forward packet by switching it to
an appropriate output port according to a routing
table. Notice that the routing table could be
updated dynamically, depending on the traffic
condition - Dynamic interconnection of input ports to output
ports - Enables dynamic sharing of transmission resource
- Two fundamental approaches
- Connectionless
- Connection-Oriented Call setup control,
Connection control, Connection release
8Packet Switching Network
- Packet switching network
- Transfers packets between users
- Transmission lines packet switches (routers)
- Origin in message switching
- Two modes of operation
- Connectionless
- Virtual Circuit
9Packet Switching - Datagram
- Messages are broken into smaller units (packets)
- Source destination addresses included in the
packet header - Datagram Connectionless, where packets are
routed independently, no dedicated path for the
data transfer phase - Packets may arrive out of order
- Pipelining of packets across network can induce
out of order, but increase system throughput
10Routing Tables in Datagram Networks
- Route determined by table lookup
- Routing decision involves finding the next hop in
the route to the given destination - Routing table has an entry for each destination
specifying output port that leads to the next hop - Size of table becomes impractical for very large
number of destinations
11Example Internet Routing
- Internet protocol uses datagram packet switching
across networks - Networks are treated as data links
- Hosts have two-port IP address
- Network address Host address
- Routers do table lookup on network address
- This reduces size of routing table
- In addition, network addresses are assigned so
that they can also be aggregated - Discussed as 8.2.5 Classless Interdomain Routing
(CIDR) in Chapter 8
12Packet Switching Virtual Circuit
- Call set-up phase establishes a fixed path along
network before the data transfer phase - All packets for the connection follow the same
path - Abbreviated header identifies connection on each
link - Packets queue for transmission
- Variable bit rates possible, negotiated during
call set-up - Delays are still variable, but will not be less
than circuit switching
13Connection Setup
- Signaling messages propagate as route is selected
- Signaling messages identify connection and setup
tables in switches - Typically a connection is identified by a local
tag, Virtual Circuit Identifier (VCI) - Each switch only needs to know how to relate an
incoming tag in one input to an outgoing tag in
the corresponding output - Once tables are setup, packets can flow along the
path
14Connection Setup Delay
- Connection setup delay is incurred before any
packet can be transferred - Delay is acceptable for sustained transfer of
large number of packets - This delay may be unacceptably high if only a few
packets are being transferred
15Virtual Circuit Forwarding Tables
- Each input port of packet switch has a forwarding
table - Lookup entry for VCI of incoming packet
- Determine output port (next hop) and insert VCI
for next link - Very high speeds are possible
- Table can also include priority or other
information about how packet should be treated
16Cut-Through switching
- Some networks perform error checking on header
only, so packet can be forwarded as soon as the
header is received processed - Delays reduced further with cut-through switching
17Chapter 7Packet-Switching Networks
- Datagrams and Virtual Circuits
- Structure of a Packet Switch
18Packet Switch Intersection where Traffic Flows
Meet
1
1
2
2
? ? ?
? ? ?
N
N
- Input ports contain multiplexed flows from access
muxs other packet switches - Flows are demultiplexed at input ports, routed
and/or forwarded to output ports - Packets buffered, prioritized, and multiplexed on
output ports
19Generic Packet Switch
- Unfolded View of Switch
- Ingress Line Card (input port)
- Header processing
- Demultiplexing
- Routing in large switches
- Controller
- Routing in small switches
- Signalling resource allocation
- Interconnection Fabric
- Transfer packets between line cards
- Egress Line Card (output port)
- Scheduling priority
- Multiplexing
20Line Cards
- Folded View
- 1 circuit board is ingress/egress line card
- Physical layer processing
- Data link layer processing
- Network header processing
- Physical layer across fabric framing
21Shared Memory Packet Switch
Output Buffering
Ingress Processing
Connection Control
1
1
Queue Control
2
2
3
3
Shared Memory
N
N
Small switches can be built by reading/writing
into shared memory
22Crossbar Switches
(b) Output buffering
(a) Input buffering
Inputs
Inputs
3
1
1
2
3
8
2
3
3
N
N
1
2
3
N
1
2
3
N
Outputs
Outputs
- Large switches built from crossbar multistage
space switches - Requires centralized controller/scheduler (who
sends to whom when) - Can buffer at input, output, or both (performance
vs complexity)
23Self-Routing Switches
- Self-routing switches do not require controller
- Output port number determines route
- 101 ? (1) lower port, (2) upper port, (3) lower
port
24Time-Division Multiplexing
- High-speed digital channel like E-carrier and
SDH, where the channel is divided into fixed
number of time slots and dedicated to some ports
- Framing required
- Telephone digital transmission
- Digital transmission in backbone network
- (a) Each signal transmits 1 unit every 3T seconds
(b) Combined signal transmits 1 unit every T
seconds
25Circuit Switches
- Circuits consist of dedicated resources in
sequence of links switches across network for
data transfer phase - Circuit switch connects input links to output
links
26Crossbar Space Switch
- N x N array of crosspoints
- Connect an input to an output by closing a
crosspoint - Nonblocking (internal blocking) Any input can
connect to idle output - Complexity N2 crosspoints
27Multistage Space Switch
- Large switch is built with multiple stages
- The n inputs to a first-stage switch share k
paths through intermediate crossbar switches - Larger k (more intermediate switches) means more
paths to output
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