Camera Electronics Box

1
SOLAR DYNAMICS OBSERVATORY

• Camera Electronics Box
• Dr N R Waltham
• CEB Lead Engineer
• n.r.waltham_at_rl.ac.uk

2
Contents

• Overview
• Team and Responsibilities
• Top-Level Requirements
• CCD Architectural Design
• CCD Readout Modes
• CCD Electronics Design Requirements
• CEB Architectural Design
• Card-Level Architectural Design
• Overview of Box Design

• Parts / Circuits
• Parts Procurement Levels
• CEB Parts
• Waveform Generator ASIC
• CCD Clock Drivers
• CDS/ADC Video Processing ASIC
• CCD Bias / DAC ASIC
• SMCSLite SpaceWire ASIC

3
Contents

• DC-DC Power Converter
• Requirements
• Options
• Grounding
• Resource Requirements
• Size
• Mass Budget
• Power Budget

• Camera EGSE
• Requirements
• Hardware
• Camera Control Software
• Image Display / Analysis Software

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CEB - Team

• RAL (Space Science and Technology Department)
• Nick Waltham Camera system design and CCD
  electronics
• Jim Lang RAL Programme Management
• Sarah Dunkin Project Management
• James King Analogue electronics / PCB design /
  Parts.
• Andy Marshall Waveform Generator ASIC / FPGA /
  digital design.
• Mathew Clapp Analogue / digital electronics
  development / test.
• Bill Duell Camera electronics (Prototyping /
  Development / test)
• Dave Parker Reliability Analysis
• Dave Smart Enclosure (box) design
• Jayne Fereday Thermal Analysis
• Dave Kelsh PA / QA
• Duncan Drummond Camera EGSE Real-Time software
• John Rainnie Camera EGSE image display / analysis
  software
• Mattias Wallner Camera EGSE test cryostat /
  electro-optics test / calibration
• RAL (Instrumentation Department Microelectronics
  Group)
• Andrea Fant Analogue ASIC design / management.
• Lawrence Jones CDS/ADC ASIC specialist.
• Bill Gannon Digital ASIC design support.

5
CEB Requirements

1. Each CEB to drive one SDO 4k x 4k pixel CCD
   through any or all of its quadrant readout ports.
   
2. CCD driver circuitry optimised for the new SDO
   E2V 4k x 4k pixel CCD.
3. CCD readout at up to 2 Mpixel/s through any or
   all of the quadrant readout ports.
4. 14 bit analogue-to-digital conversion with
   programmable video gain and video offset.
5. Video digitisation sensitivity and dynamic range
   matched to an anticipated CCD full well capacity
   of 150-200k electrons, and a CCD readout noise of
   ? 25 electrons rms.
6. Programmable CCD readout waveform patterns,
   sequences, and readout modes.
7. Windowed readout of at least two windows, and
   pixel summing options.
8. Software control of critical CCD bias voltages
   (TBC).
9. Interface to the HEB via the SpaceWire Adaptation
   of IEEE1355.
10. Camera Enclosure to be as small and light-weight
    as possible.
11. EEE Components to be GSFC 311-INST-001.
12. Components to be radiation tolerant to gt 35 Krads
    total dose (inside box with 5mm walls).
13. Components to be latch-up free otherwise
    protected with latch-up current trips.

6
CEB Requirements

• Operationally, the camera will provide at least
  the following modes
• CLEAR
• Fast CLEAR through CCD Dump-Drain
• Flexible CLEAR routine by appropriate programming
  of the CEBs waveform generator. 
• EXPOSURE
• CCDs image area clocks held at appropriate
  voltage levels.
• Serial register clocks can be individually
  programmed to be high, low, or clocking.
•  
• READOUT
• Flexible READOUT routines by appropriate
  programming of the CEBs waveform generator.
• Readout through all four ports, two ports, or one
  port.
• Windowed readout of at least two windows.
• Full-frame, or windowed readout with n x m pixel
  summing.
• Continuous clocking.  

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CCD Architectural Design and Readout Modes
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Electronics Design Requirements - Thin-Oxide CCD
CCD Clocks No. of Drivers Voltage Function
8 Channels 7-8 V 4 Phase Imaging Area
(top and bottom) 2 Channels 7-8 V
Transfer Gate (top and bottom) 1 Channel
7-8 V Dump Gate (top and bottom) 5
Channels 5 V 3 Phase Serial register
(left and right) 1 Channel 5 V Summing
Well (left and right) 1 Channel 10 V
Reset Clock Bias Voltages OD 1 Channel 23
V Output Transistor Drain RD 1 Channel 14
V Reset Transistor Drain SS 1 Channel 0-9
V Substrate Voltage DD 1 Channel 24 V Dump
Drain OG1 1 Channel 2 V Output Gate 1 OG2 1
Channel 3 V Output Gate 2 Notes 1. Separate
OD, RD (and JD) drivers for each output to
minimise crosstalk. 2. Software Control of bias
voltages incorporated within baseline design.
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CEB Architectural Design
SpaceWire Interface
4 x CDS/ADC Video Processor ASICs
LVDS for high speed data/clocks down backplane
ASIC Timing Generator
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Architectural Design - CCD Video Card
Video Data Mux
CDS/ADC ASIC
LVDS Data transmission down backplane at 16 MHz
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Architectural Design - CCD Driver Card
Image Area, Serial Register and Reset Clock
Drivers
Waveform Generator ASIC
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Architectural Design - CCD Bias Card
Low Noise CCD Bias Drivers
Software Bias Control
H/K Telemetry Mux
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Architectural Design - SpaceWire Card
LVDS Backplane signals
SMCSLite SpaceWire ASIC
200 Mbits/s Link Rate
16k word 16 bit wide FIFO Buffer
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Architectural Design - Power Converter
In-Rush Current Limiter and Current Trip
Input Filter
M3GT280515T or ART2815T DC-DC Converter
Output Filter
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Overview of Box Design
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Overview of Box Design
PCBs added
PCBs screwed down to side rails
Dog House Cover added
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Overview of Box Design
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Parts / Circuits

• Overview of EEE Parts Specification
• Waveform Generator ASIC
• CCD Clock Drivers
• CDS/ADC Video Processing ASIC
• DAC ASIC
• SMCSLite SpaceWire ASIC
• DC-DC Converter

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EEE Part Specification

• Parts Procurement Levels
• ICs MIL-PRF-38535 QML-Level V (preferred),
  QML-Level Q, or up-screened MIL-STD-883-B
  PIND Life-Test (minimum)
• RAL ASICs 0.35?m radiation-tolerant CMOS (from
  AMS).
• Packaging to Mil Std 883E 5004 Class B plus
  PIND.
• Actives Transistors/Diodes JANTXV (minimum),
  JANS (Interface parts).
• Passives Resistors MIL-R-55342, or
  equivalent, Capacitors MIL-C-55681/55365, or
  equivalent,
• Connectors Micro-D MIL-PRF-83513, or
  equivalent, Standard-D MIL-PRF-24308 , or
  equivalent, Backplane MIL-PRF-55302
• Radiation Issues
• 100 krad, latch-up free parts where possible,
  and gt 35 krad parts in all other cases.
• Latch-up protection for parts / sub-systems
  below minimum SEL threshold.
• All parts except ASICs procured by LMSAL through
  EEE Parts Control Board.

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RAL Waveform generator ASIC

• Single chip to generate all the timing signals
  needed to read out a CCD

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RAL WGS2003 ASIC Features

• Up to 32-bit wide logic Waveform pattern
  generation.
• 80MHz output pattern rate.
• Waveform Output Inversion Register to program
  polarity of each Waveform output.
• 8-bit wide Waveform dwell function for each
  Waveform state.
• Up to 32 configurable Waveform patterns.
• Seamless Waveform pattern generation under the
  control of Table sequences.
• Up to 32 configurable Table sequences.
• Parameter specified (up to 65535) or endless
  looping of Wave sequences.
• Nested looping of Wave sequences, with a
  nested-loop depth of up to four.
• Halt, externally triggered re-start, Table
  synchronization output and jump instruction for
  exotic control sequences.
• Programming via a 3 wire serial I2C interface
  running at up to 1Mbit/sec.
• Auto incrementing memory programming function to
  speed up RAM programming.
• RAM Double bit error detection and single bit
  error correction using hamming code.
• Status register to show Waveform/Table activity,
  Detected errors, etc.
• RAM self-test function to check every memory
  location for errors.

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RAL WGS2003 ASIC Block Diagram
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RAL WGS2003 ASIC Implementation

• Design
• Synchronous Design in VHDL.
• Prototyping target ACTEL Axcelerator FPGA
• Flight target (Baseline)
• ACTEL RTAX2000S
• Straight forward translation from Axcelerator to
  RTAX2000S.
• Projected 200 krads total dose and
  Single-Event-Latch-up (SEL) immunity.
• Eliminates ASIC packaging / testing /
  up-screening risks.
• Physically large package.
• Availability ?
• or
• AMS 0.35µm ASIC on AMS (austriamicrosystems)
  0.35µm C35 OPTO CMOS
• Smaller dedicated package.
• FPGA-to-ASIC translation / packaging / testing /
  up-screening / schedule issues.
• AMS 0.35µm C35 OPTO (20 µm epitaxial CMOS)
  process SEL threshold ?

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RAL WGS2003 ASIC ACTEL RTAX2000S
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CCD Clock Drivers Requirements and Solutions

• 5 V Serial Register Clock Drivers Intersil
  ACTS245 QML-V 300 krads SELth gt 100MeV
• 3-phase clocks at 2 MHz.
• 750 pF loading per phase ( 5x SECCHI CCD).
• 9-10 V Reset Clock Driver. Unitrode UC1708
  QML-V bipolar part, Radiation ?
• 50ns-100ns pulse at 2 MHz repetition rate.
• few pF loading.
• 7-8 V Imaging Area Clock Drivers Intersil
  ISL74422ARH QML-V 300 krads SEL immune
• 4-phase clocks at 10 KHz
• 100 nF loading per phase .
• 7-8 V Transfer / Dump Gate Clock Drivers
  Intersil ISL74422ARH
• 10 KHz / 1 Hz clocks.
• 2500 pF loading.

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Serial Register Clock Drivers
Clocking SECCHI CCD42-40 additional load
capacitors
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RAL CDS/ADC ASIC
Features DC Restoration of the CCD video
signal. Fully differential-input preamplifier and
CDS. 1 V video signal input range. Fully
differential pipelined 16 bit ADC with digital
error correction. Operation at up to at least 1
Mpixels/s readout rate. 10 bit Programmable
Offset (/- 500 mV). 7 bit Programmable Gain
(gain x 1 to x 3). Input referred system noise
? 3.2 adu rms. 3-wire serial interface to program
video gain and offset. Triple-voting internal
control Logic to protect against single-event
upsets (SEUs). Single 3.3 V power supply. Supply
current 125 mA. 0.35 ?m CMOS process. 84-pin
CQFP with 0.025 inch lead pitch.
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CDS/ADC Video Processing

• RAL SECCHI CDS/ADC ASIC
• 1 Mpixels/s CCD preamplifier, CDS processor and
  ADC.
• Input noise 0.75 ADU rms 1V input range.
• 125mA _at_ 3.3V _at_ 1 Mpixels/s 625mW from 5V
  x4 for SDO.
• Radiation tolerant, but bulk AMS 0.35?m CSI CMOS
  process (Latch-up sensitive).
• New Features for SDO
• Operation up to 2 Mpixels/s readout rate.
• AMS 0.35 ?m C35 OPTO (20 µm epitaxial) process
• Better SEL threshold?

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CCD Bias / DAC ASIC
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CCD Bias / DAC ASIC
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CCD Bias / DAC ASIC
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SMCSLite SpaceWire ASIC
http//www.estec.esa.nl/microelectronics/presentat
ion/SMCSLite
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SMCSLite SpaceWire ASIC
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DC-DC Power Converter

• Requirements
• 28V Primary Input with in-rush current
  limiting.
• 5V, 3.3V, and 2.5V for logic (3.3V and 2.5V
  rails to be derived from 5V).
• 3.3V for ASICs (3.3V rail to be derived from
  5V).
• 5V for CCD Serial Register Clock Driver
  supplies.
• 15V for CCD Image Area / Dump Gate Clock Driver
  supplies.
• 30V for CCD biasing.
• Secondary side filtering of all power.
• Good regulation, low noise, sufficient power,
  and maximum conversion efficiency.
• Radiation hard or radiation tolerant design.
• Design / Configuration
• Triple rail (5V, /-15V) module configured as
  5V, 15V, 30V.

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DC-DC Power Converter
36
DC-DC Power Converter

• Power Conversion and Filtering Design
• Hybrid modular DC-DC converter - M3GT280515T
  (Baseline) or ART2815T
• EMI filter to provide common mode and
  differential filtering.
• In-rush current limiting / current trip circuit
  before EMI filter.
• Common mode and differential filtering on
  secondary rails at outputs of DC-DC converter
• Grounding
• Primary power isolated within CEB
• Secondary power returns connected to chassis
  throughout box.

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CEB Resource Requirements

• Volume 150 mm x 131 mm x 95 mm
• (excluding mounting feet and connector
  extrusions).
• Mass 2.95 kgs (no contingency added).
• Power 11.4 W (exposure), 15.0 W (readout) with
  JFETs
• 10.7 W (exposure), 14.3 W (readout) without
  JFETs
• (no contingency added).
• TC/TM Hardware Standard SpaceWire Adaptation of
  IEEE1355 With LVDS Signals.
• TC/TM Data Rate 200Mbits/s.
• Power Connector 9-Way Standard-D Connector
  (Plug).
• TC/TM Connector 9-Way MDM Micro-D Connector
  (Socket).
• CCD Connector(s) 21S, 25P, 31P MDM Micro-D
  Connectors.
• Synchronisation None needed.
• Temperatures -10C to 40C Operating
  Temperature Range.
• -20C to 50C Survival Temperature Range.

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Mass Budget
39
Power Budget
40
Camera EGSE Requirements

• Enhanced STEREO/SECCHI system for 4-port 4k x 4k
  SDO CCD readout.
• IDL Image Display running on LINUX-based PC.
• Camera programming and set-up (Waveforms, Readout
  tables, Video gain / offset).
• Camera Control i.e., CLEAR, Exposure, Readout
  commands.
• Image display and adjustment of grey levels.
• Zoom window with adjustable zoom factor.
• Saving of images to disc in FITS format, and
  recalling images from disc.
• Basic low-level image processing functions (i.e.,
  addition, subtraction, and division of any 2
  images).
• Feature extraction.
• Basic statistical analysis of the extracted image
  data including mean pixel value, max pixel value,
  min pixel value, variance and RMS values.
• Profile plotting through image data.

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CEB EGSE Hardware - Options

• SpaceWire Interfaces to PCs
• 4Links PCI Card (as used in STEREO / SECCHI)
• Based on SMCS332 (big brother of SMCSLite).
• 3 Links with theoretical 200 Mbits/s rate.
• Linux and Win2k Drivers (SECCHI uses LINUX).
• Only works if CCD Line transfer time is 250 µs
• i.e. Effective throughput 16 Mbytes/s.
• University of Dundee 8Links / USB2 Box
• FPGA Design.
• 8 Links.
• Throughput achieves 16 Mbytes/s (with the right
  PC!)
• Need PC with DMA (SCSI) discs.

Baseline for SDO
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Camera Control SoftwareCamera Control Panel

• Camera Setup Window
• Waveform/Table Load File Source
• Set Video Gain/Offset
• Reset Buttons
• Clear CCD Command
• Exposure Command
• Read CCD Command

• Camera Setup Window
• Table Number Assignment to Clear/Readout Commands
• Data Dump-File Details

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Image Display / Analysis Software