CCD Camera Design

1
CCD Camera Design

• Chris McFee
• Mullard Space Science Laboratory

2
Introduction

• Science drivers for CCD camera design
• CCD features
• Camera Mechanical Design
• Camera Electronic Design
• Camera Design Trade Offs
• Challenges
• Test Plan and Facilities

3
CCD Camera Assembly

• The Camera Assembly consists of
• Focal Plane Assembly (FPA).
• Two CCDs at focal plane
• Mechanical mounting of CCDs at focal plane
• Read Out Electronics.
• Three Flight Model CCDs procured with option for
  further CCDs.
• Three Engineering models and six Commercial
  Devices.

4
CCD Camera Requirements
Heading Requirement Camera Implications
Spectral resolution High CCD pixel size 13.5µm. Minimisation of charge transfer inefficiency. Minimisation of the effects of radiation induced dark noise.
Spatial resolution Equal to or less than 2 CCD pixel size 13.5µm.
5
CCD Camera Requirements
Heading Requirement Camera implications
Temporal Resolution High temporal resolution for both imaging and spectroscopy Readout speed of 500 kpixels/s. On chip windowing. Provision of dump drain.
Wavelength range Two wavelength ranges Two CCDs. Backthinned to maximise QE
6
CCD Camera Requirements
Heading Requirement Camera Implications
Read out Read out fractions of the CCD Windowing will be implemented
Read out Read out in fractions of a second Readout speed of 500 kpixels/s On chip windowing Provision of dump drain
7
CCD features

• Marconi (EEV) 42-20
• Size 2048x1024 (13.5µm square pixels)
• MPP device (dark noise 300 e/p/s _at_ 20C)
• Basic backthining process - 80 QE
• Electronic readnoise 5/6 electrons
• Full well - 90k electrons (7000 photons)
• Two readout amplifiers per CCD.

8
CCD Camera Mechanical design

• CCDs mechanically supported at Focal plane
• CCDs bonded to individual invar plates
• These invar plates then attached to backplates
  built at MSSL
• Can be moved in two dimensions for alignment
• CCDs connected to ROE by short cable to minimise
  noise pickup.

9
CCD Camera Design

• Operating temperature -55 C
• CCD can be heated to 30 C to remove
  contamination
• Three phase clocking
• Up to two windows per CCD
• Gain 5.5 electrons per DN
• Binning in spatial and spectral direction
• Dumping of unwanted lines
• Programmable voltages to minimise the effects of
  ionising radiation damage
• Overclocking for testing, offset bias
  determination, etc.
• Stim patterns for testing
• Flat fielding/Pre flash LEDs.

10
CCD Camera Design

• Status monitoring.
• CCD temperatures
• Current monitoring of supply lines
• Voltage monitoring of supply lines
• Monitor voltage of substrate bias, reset drain
  bias and output drain bias
• Reflect back register values for check.

11
CCD Camera Design

• Science data via high speed link
• Communication with ICU via LVDS drivers
• _at_ 16 Mbits/s for each data link
• Commands and Status information via low speed
  link
• _at_ 9.6 k baud

12
CCD Camera Design
Window counters
Science data
Image clocks
Readout clocks
Sync
High Speed Link
Variable bias Vrd, Vod, Vss
Sample and convert logic
CCD bias
Low Speed Link
CCD 0
Parallel to Serial conversion
Pre-amplification
ADC
Commands and status
CCD 1
13
CCD Camera Design Trade Offs

• Operating temperature
• low operating temperature to minimise dark
  current and the potential effects of radiation
  damage. But very low temperatures difficult to
  obtain without major redesign of radiator,
  requires use of MPP device but this lowers the
  full well capacity
• Shielding
• maximise shielding to minimise radiation damage
  but this will add mass. Use of programmable
  voltages minimises the effects of this damage.

14
CCD Camera Design Trade Offs

• Read Out Rates.
• 500 kpixels/s baselined. Faster readouts are
  difficult to achieve in current power budget and
  design and faster readout also increases CCD
  readout noise
• On Chip windowing.
• Design of electronics is greatly simplified by
  reducing the number of windows that are
  available
• Mass
• Shielding.

15
CCD Camera Challenges

• Cleanliness EUV demands extreme cleanliness
• All operations will use at least a class 100
  cleanroom or better, high standards from GOES-SXI
  programme adopted with great care taken to
  eliminate molecular contamination
• Readout speed current designs 330 kpixels/s
• 500 kpixels/s and 14 bit digitisation challenging
  but achievable
• Physically fitting electronics within the ROE box
  constraints.

16
CCD Camera Test Plan

• Read out electronics
• Verification of correct functionality
• Optimisation of design with CCD
• Read out noise
• Validate grounding
• CCD characterisation
• Establish and Monitor chamber cleanliness levels
• Defects, hot pixels, QE
• Integration with spectrometer

17
Current CCD Camera Test Facilities

• Camera Test Facilities based on Facilities
  developed for GOES/SXI
• (large amount of redundancy available)

18
Current CCD Camera Test Facilities
PC 500 MHz, 128Mb ram
Read out Electronics
CCD
DAC card CCD bias control ADC Card CCD bias
monitoring DMA Card MSSL built ISA Card Control
of clocking Receive CCD data via high speed link
(5.2 MHz) Generate CCD commands via low speed
link (64 kbaud) Generate bilevel command
lines and receive status lines
Bias Control box
Card 1 CCD bias supplies Power
switching Amp-cds-adc Card 2 Clock pulse
generator Card 3 Interface to PC (FIFO-PISO-HSL)
Control of CCD bias voltages Monitor CCD
voltages Control image clocks
Focal plane Assembly Preamps Clock level shifters
19
CCD Camera Schedule

• CCD Camera completed 20 December 2000
• PM delivery 12 March 2001.

20
Summary

• Resolution.
• pixel size 13.5µm.
• MPP device to minimise dark current
• Temporal resolution.
• Readout rate 500 kpixels/s
• Dump drain facility
• On-chip windowing
• Two readout amplifiers per CCD.