State Machine

1
State Machine Timing Design
2
?? ??

• Finite State Machine(FSM)
• Mealy Machine
• Moore Machine
• FSM in VHDL
• More VHDL codes for FSMs
• Techniques for simple sequential logic design

3
Finite State Machines (FSMs)

• Any circuit with memory is a finite state machine
  (FSM?? ?? ??)
• Even computers can be viewed as huge FSMs
• Design of FSMs involves
• Defining states
• Defining transitions between states
• Optimization / minimization
• Manual optimization/minimization is practical for
  small FSMs only

4
Moore FSM

• Output is a function of a present state only

5
Moore Machine
transition condition 1
state 2 / output 2
state 1 / output 1
transition condition 2
6
Mealy FSM

• Output is a function of a present state and inputs

7
Mealy Machine
transition condition 1 / output 1
state 2
state 1
transition condition 2 / output 2
8
Moore vs. Mealy FSM (1)

• Moore and Mealy FSMs can be functionally
  equivalent
• Equivalent Mealy FSM can be derived from Moore
  FSM and vice versa
• Mealy FSM has richer description and usually
  requires smaller number of states
• Smaller circuit area

9
Moore vs. Mealy FSM (2)

• Mealy FSM computes outputs as soon as inputs
  change
• Mealy FSM responds one clock cycle sooner than
  equivalent Moore FSM
• Moore FSM has no combinational path between
  inputs and outputs
• Moore FSM is more likely to have a shorter
  critical path

10
Moore FSM - Example 1

• Moore FSM that recognizes sequence 10

11
Mealy FSM - Example 1

• Mealy FSM that recognizes sequence 10

12
Moore Mealy FSMs Example 1
13
FSMs in VHDL

• Finite state machines can be easily described
  with processes
• Synthesis tools understand FSM description if
  certain rules are followed
• State transitions should be described in a
  process sensitive to clock and asynchronous reset
  signals only
• Outputs described as concurrent statements
  outside the process

14
State Machine - Mealy Machine

• Mealy Machine
• ??? ??(Current State)? ??? ??(Inputs)? ?? ??? ???

15
Mealy FSM ? ?? State diagram
?? 1. WindowAct??? 0?? 1? ??? S1 state?? ??, ? ?
output RiseShot? 1?, 2. WindowAct??? 1?? 0?? ???
S0 state?? ??, FallShot? 1? ???? ?. 3. State ???
??? output?? ?? 0
16
Mealy Machine ?? Process 2???
Library ieee Use ieee.std_logic_1164.all ENTITY
RiseFallShot IS PORT( clk IN STD_LOGIC res
et IN STD_LOGIC WindowAct
IN STD_LOGIC RiseShot, FallShot
OUT STD_LOGIC) END RiseFallShot ARCHITECTURE a
OF RiseFallShot IS TYPE STATE_TYPE IS (s0,
s1) SIGNAL state STATE_TYPE BEGIN PROCESS
(clk, reset) BEGIN IF reset '0' THEN
state lt s0 ELSIF clk'EVENT AND clk
'1' THEN CASE state IS WHEN s0 gt
IF WindowAct'1' THEN state lt s1
ELSE state lt s0 END
IF WHEN others gt IF WindowAct'0'
THEN state lt s0 ELSE state
lt s1 END IF END CASE END
IF END PROCESS
??? Data type STATE_TYPE ??
?? ??
Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
17
Mealy Machine ?? Process 2? ??
PROCESS(state, WindowAct) BEGIN if(
state s0 and WindowAct'1') then
RiseShot lt'1' else RiseShot
lt'0' end if if( state s1 and
WindowAct'0') then FallShot lt'1'
else FallShot lt'0' end
if END PROCESS END a
Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
?? ??
18
Mealy Machine ?? Process 3? ??
library ieee Use ieee.std_logic_1164.all ENTITY
RiseFallShot_v2 IS PORT( clk
IN STD_LOGIC reset IN STD_LOGIC WindowA
ct IN STD_LOGIC RiseShot, FallShot
OUT STD_LOGIC) END RiseFallShot_v2 ARCHITECTURE
a OF RiseFallShot_v2 IS TYPE STATE_TYPE IS (s0,
s1) SIGNAL State, NextState STATE_TYPE BEGIN
PROCESS (State, WindowAct) BEGIN CASE State
IS WHEN s0 gt IF WindowAct'1'
THEN NextState lt s1 ELSE NextState
lt s0 END IF WHEN others gt IF
WindowAct'0' THEN NextState lt
s0 ELSE NextState lt s1 END
IF END CASE END PROCESS
?? ??
Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
19
Mealy Machine ?? Process 3? ??
PROCESS(reset,clk) BEGIN IF reset '0'
THEN State lt s0 ELSIF clk'EVENT AND clk
'1' THEN State lt NextState END IF END
PROCESS process(State,WindowAct) begin
if( State s0 and WindowAct'1') then
RiseShot lt'1' else
RiseShot lt'0' end if if(
State s1 and WindowAct'0') then
FallShot lt'1' else
FallShot lt'0' end if end
process
?? ??
Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
?? ??
20
State Machine - Moore Machine

• Moore Machine
• ??? ??(Current State)?? ?? ??(Outputs)? ???
• Moore is less

Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
21
Moore Machine ?? State diagram
?? ??
?? WindowAct ?? y(20)
?? 1. WindowAct??? 0? ?? State? ??? ???, 1? ??
state? ??? S0-gtS1-gtS2-gtS0? ????. 2. ???? y(20)?
??? S0? ?? 000? S1? ???? 010? S2? ???? 101?
????.
22
Moore Machine ?? Process 2? ??

• Library ieee Use ieee.std_logic_1164.all
• ENTITY MooreMachine IS
• PORT( clk, reset, WindowAct IN STD_LOGIC
• y OUT STD_LOGIC_vector(2 downto 0))
• END MooreMachine
• ARCHITECTURE a OF MooreMachine IS
• TYPE STATE_TYPE IS (s0, s1,s2)
• SIGNAL state STATE_TYPE
• BEGIN
• PROCESS (clk, reset)
• BEGIN
• IF reset '0' THEN
• state lt s0
• ELSIF clk'EVENT AND clk '1' THEN
• CASE state IS
• WHEN s0 gt
• IF WindowAct'1' THEN state lt s1

?? ??
Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
23
Moore Machine ?? Process 2? ??

• PROCESS(state)
• BEGIN
• CASE state IS
• WHEN s0 gt
• y lt "000"
• WHEN s1 gt
• y lt "010"
• WHEN others gt
• y lt "101"
• END CASE
• END PROCESS
• END a

Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
?? ??
24
Moore Machine ?? Process 3? ??

• Library ieee Use ieee.std_logic_1164.all
• ENTITY MooreMachine_v3 IS
• PORT( clk, reset, WindowAct IN STD_LOGIC
• y OUT STD_LOGIC_vector(2 downto 0))
• END MooreMachine_v3
• ARCHITECTURE a OF MooreMachine_v3 IS
• TYPE STATE_TYPE IS (s0, s1,s2)
• SIGNAL state, NextState STATE_TYPE
• BEGIN
• PROCESS ( State, WindowAct)
• BEGIN
• CASE State IS
• WHEN s0 gt
• IF WindowAct'1' THEN NextState lt s1
• ELSE NextState lt s0
• END IF
• WHEN s1 gt

?? ??
Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
25
Moore Machine ?? Process 3? ??
?? ??

• PROCESS (clk, reset)
• BEGIN
• IF reset '0' THEN
• state lt s0
• ELSIF clk'EVENT AND clk '1' THEN
• state lt NextState
• END IF
• END PROCESS
• PROCESS(state)
• BEGIN
• CASE state IS
• WHEN s0 gt
• y lt "000"
• WHEN s1 gt
• y lt "010"
• WHEN others gt
• y lt "101"

Current State
Combinational Logic
F/F
Next State
Inputs
Combinational Logic
Outputs
?? ??
26
Moore FSM
process(clock, reset)
Next State function
Inputs
Next State
Present StateRegister
clock
Present State
reset
concurrent statements
Output function
Outputs
27
Mealy FSM
process(clock, reset)
Next State function
Inputs
Next State
Present State
Present StateRegister
clock
reset
Output function
Outputs
concurrent statements
28
Moore FSM - Example 1

• Moore FSM that Recognizes Sequence 10

29
Moore FSM in VHDL (1)
TYPE state IS (S0, S1, S2) SIGNAL Moore_state
state U_Moore PROCESS (clock,
reset) BEGIN IF(reset 1) THEN Moore_state
lt S0 ELSIF (clock 1 AND clockevent)
THEN CASE Moore_state IS WHEN S0 gt IF
input 1 THEN Moore_state
lt S1 ELSE
Moore_state lt S0 END IF
30
Moore FSM in VHDL (2)

• WHEN S1 gt
• IF input 0 THEN
• Moore_state
  lt S2
• ELSE
• Moore_state
  lt S1
• END IF
• WHEN S2 gt
• IF input 0 THEN
• Moore_state
  lt S0
• ELSE
• Moore_state
  lt S1
• END IF
• END CASE
• END IF
• END PROCESS
• Output lt 1 WHEN Moore_state S2 ELSE 0

31
Mealy FSM - Example 1

• Mealy FSM that Recognizes Sequence 10

32
Mealy FSM in VHDL (1)
TYPE state IS (S0, S1) SIGNAL Mealy_state
state U_Mealy PROCESS(clock,
reset) BEGIN IF(reset 1) THEN Mealy_state
lt S0 ELSIF (clock 1 AND clockevent)
THEN CASE Mealy_state IS WHEN S0 gt
IF input 1 THEN
Mealy_state lt S1 ELSE
Mealy_state lt S0
END IF
33
Mealy FSM in VHDL (2)

• WHEN S1 gt
• IF input 0 THEN
• Mealy_state
  lt S0
• ELSE
• Mealy_state
  lt S1
• END IF
• END CASE
• END IF
• END PROCESS
• Output lt 1 WHEN (Mealy_state S1 AND input
  0) ELSE 0

34
Moore FSM Example 2 State diagram
35
Moore FSM Example 2 State table
36
Moore FSM with 2s Processes
process(clock, reset)
Input w
Next State function
Next State
Present StateRegister
Present State y
clock
resetn
Output z
concurrent statements
Output function
37
Moore FSM Example 2 VHDL code (1)
USE ieee.std_logic_1164.all ENTITY simple
IS PORT ( clock IN STD_LOGIC
resetn IN STD_LOGIC
w IN STD_LOGIC z
OUT STD_LOGIC ) END simple ARCHITECTURE
Behavior OF simple IS TYPE State_type IS (A, B,
C) SIGNAL y State_type BEGIN PROCESS (
resetn, clock ) BEGIN IF resetn '0'
THEN y lt A ELSIF (Clock'EVENT AND Clock
'1') THEN
38
Moore FSM Example 2 VHDL code (2)
CASE y IS WHEN A gt IF w '0' THEN
y lt A ELSE y lt B
END IF WHEN B gt IF w '0'
THEN y lt A ELSE y lt C
END IF WHEN C gt IF w '0'
THEN y lt A ELSE y lt C
END IF END CASE
39
Moore FSM Example 2 VHDL code (3)

• END IF
• END PROCESS
• z lt '1' WHEN y C ELSE '0'
• END Behavior

40
Moore FSM with 3s Processes
process (w, y_present)
Input w
Next State function
Next State y_next
process (clock, resetn)
Present StateRegister
Present State y_present
clock
resetn
Output z
concurrent statements
Output function
41
Alternative VHDL code (1)
ARCHITECTURE Behavior OF simple IS TYPE
State_type IS (A, B, C) SIGNAL y_present,
y_next State_type BEGIN PROCESS ( w,
y_present ) BEGIN CASE y_present IS WHEN A
gt IF w '0' THEN y_next lt A
ELSE y_next lt B END IF
WHEN B gt IF w '0' THEN y_next lt
A ELSE y_next lt C END IF
42
Alternative VHDL code (2)
WHEN C gt IF w '0' THEN y_next lt A
ELSE y_next lt C END IF END
CASE END PROCESS PROCESS (clock,
resetn) BEGIN IF resetn '0'
THEN y_present lt A ELSIF (clock'EVENT AND
clock '1') THEN y_present lt y_next END
IF END PROCESS z lt '1' WHEN y_present C
ELSE '0' END Behavior
43
Mealy FSM Example 2 State diagram
44
Mealy FSM Example 2 State table
45
Mealy FSM with 2s Processes
process(clock, reset)
Input w
Next State function
Next State
Present State y
Present StateRegister
clock
resetn
Output z
Output function
concurrent statements
46
Mealy FSM Example 2 VHDL code (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY Mealy IS PORT ( clock IN
STD_LOGIC resetn IN
STD_LOGIC w IN
STD_LOGIC z OUT STD_LOGIC ) END
Mealy ARCHITECTURE Behavior OF Mealy IS TYPE
State_type IS (A, B) SIGNAL y State_type
BEGIN PROCESS ( resetn, clock ) BEGIN IF
resetn '0' THEN y lt A ELSIF
(clock'EVENT AND clock '1') THEN
47
Mealy FSM Example 2 VHDL code (2)

• CASE y IS
• WHEN A gt
• IF w '0' THEN
• 
  y lt A
• ELSE
• 
  y lt B
• END IF
• WHEN B gt
• IF w '0' THEN
• 
  y lt A
• ELSE
• 
  y lt B
• END IF
• END CASE

48
Mealy FSM Example 2 VHDL code (3)

• END IF
• END PROCESS
• WITH y SELECT
• z lt w WHEN B,
• z lt 0 WHEN others
• END Behavior

49
Timing Design - ????

• State Machine ??
• Shift Register ??
• Counter ??

??? ??????? ??? ???? ??? ??? ??? ?? ??? ?? ????.
?? ????? ??? ??? ???? ??? ?? ??? ?? ?? ??? ???
????.
50
Timing Design State Machine Application (1)
1. ??? ?? Timing ??? ??? ?? ??? ?????

• ?? WindowAct??? 0?? 1? ??? ???? ?? clock?
  rising edge ?? RiseShot? 1? ???
• WindowAct??? 1?? 0?? ??? ???? ?? clock? rising
  edge ?? FallShot? 1? ???? ?.

51
Timing Design State Machine Application (2)
2.Excercise Mealy-machine state diagram? ????
WindowAct / RiseShot, FallShot
?? / ??1, ??2
52
Timing Design State Machine Application (3)
????? ??? ?? ??? ???? ??
53
Timing Design State Machine Application (4)
????? ??? ?? ??? ???? ??
Note The outputs react to input asynchronously.
54
Timing Design State Machine Application (5)

• Result

55
Timing Design State Machine Application (6)
3. ???? ???? ?? ?? ??? ? ? Timing ?? ??? ??
1
3
4
2
1,3 ?? RiseShot WindowAct and Q
Q? WindowAct? D F/F?? ???? ??
2,4 ?? FallShot WindowAct and Q
56
Timing Design State Machine Application (7)
3. Timing ?? ??? ???? - BDF
Q? WindowAct? D FF?? ???? ??
WindowAct and Q
not Q
not WindowAct
WindowAct and Q
57
Timing Design State Machine Application (8)
library ieee use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity
RiseFallShot_time is port( WindowAct in
std_logic clk,nclr in std_logic
RiseShot,FallShot out std_logic ) end
RiseFallShot_time architecture a of
RiseFallShot_time is signal q
std_logic signal RisingShotPules
std_logic begin -- shift register 1bits
process(nclr,clk) begin if( nclr'0')
then q lt'0' elsif(clk'event and clk'1')
then q lt WindowAct end if end
process -- rising shot pulse gen. RiseShot lt
WindowAct and not q FallShot lt not WindowAct
and q end a
3. Timing ?? ??? ???? - VHDL
?? ??
?? ??
58
Timing Design Shift Register Application (1)

• ??? ?? Timing ??? ??? ?? ??? ?????.
• ???? reset, clk, WindowAct
• ???? y0, y1, y2, y3, y4, y5, y6

59
Timing Design Shift Register Application (2)
1. ?? ??? ??? ?????. ???? reset, clk,
WindowAct ???? y0
?? ???? ???? ???? ? 1???? ??? ? ?? ??? Shift
Register? ???? ??
60
Timing Design Shift Register Application (3)
???? y0? Q1? 1? ?? ??? Q2? 0? ?? 700-900ns???? 1?
??. Y0Q1 and Q2
??? ?? Shift Register? ???? ?? Q0, Q1, Q2? ????
??? ? ??.
Y0 Q1 and not Q2
61
Timing Design Shift Register Application (4)
2. ???? y1? ?????.
62
Timing Design Shift Register Application (5)
Y0? clk? falling edge? ???? shift?? ??? shift?
Y1? ?? ? ??.
63
Timing Design Shift Register Application (6)
3. ???? y2? ?????.
64
Timing Design Shift Register Application (7)
Y2? Y0? Y1? OR ? ??? ? ? ??. Y2 Y0 or Y1
Y2 Y0 or Y1
65
Timing Design Shift Register Application (8)
4. ???? y3? ?????.
66
Timing Design Shift Register Application (9)
11 bits Shift Register
Y3? 11?? shift register??? Q9? 1?? Q10? 0? ??? 1?
???? ??.
67
Timing Design Shift Register Application (10)
Y3? 11?? shift register??? Q10? Q9? ??? ???. Y3
Q9 and Q10
68
Timing Design Shift Register Application (11)
5. ???? y4? ?????.
69
Timing Design Shift Register Application (12)
Y4? Y1? Y3? OR ? ??? ? ? ??. Y4 Y1 or Y3
70
Timing Design Shift Register Application (13)
6. ???? y5? ?????.
71
Timing Design Shift Register Application (14)
Y5? Q2? 1?? Q10? 0? ??? 1? ??.
72
Timing Design Shift Register Application (15)
7. ???? y6? ?????.
73
Timing Design Shift Register Application (16)
Y6p? Q1? 1?? Q9? 0? ??? 1? ??.
Y6? Y6p? Clk? Falling Edge? ???? ? ?? ??? ???.
74
Timing Design Shift Register Application (17)

• library ieee
• use ieee.std_logic_1164.all
• use ieee.std_logic_unsigned.all
• entity shift_app2 is
• port( clk,nclr,WindowAct in std_logic
• y buffer std_logic_vector(0 to 6))
• end shift_app2
• architecture a of shift_app2 is
• signal q std_logic_vector(0 to 10)
• signal y6p std_logic
• begin
• ShiftRegster
• process(nclr,clk)
• begin
• if( nclr'0') then
• qlt"00000000000"
• elsif(clk'event and clk'1') then
• q(0)lt WindowAct
• for i in 0 to 9 loop

????
????
75
Timing Design Shift Register Application (18)
????

• process(nclr,clk)
• begin
• if( nclr'0') then
• y(1)lt'0'
• elsif(clk'event and clk'0') then
• y(1)lty(0)
• end if
• end process
• y(2) lt y(0) or y(1)
• y(3) lt q(9) and not q(10)
• y(4) lt y(1) or y(3)
• y(5) lt q(2) and not q(10)
• y6p lt q(1) and not q(9)
• process(nclr,clk)
• begin
• if( nclr'0') then
• y(6)lt'0'

????
????
76
Timing Design Result (1)
77
Timing Design Result (2)
78
Timing Design Resource Usage
79
Timing Design Counter Application (1)

• ??? ?? Timing ??? ??? ?? ??? Shift Register? ??
  ?? ??(Counter??)?? ?????.
• ???? reset, clk, WindowAct
• ???? y0, y1, y2, y3, y4, y5, y6

80
Timing Design Counter Application (2)
1. ???? ???? cnt3..0? ?? ? ????
81
Timing Design Counter Application (3)
? ???? WindowAct? 1? ?? ????, WindowAct? 0? ??
0?? ??.
process(nclr,clk) begin if( nclr'0')
then cntlt"0000" elsif(clk'event and
clk'1') then if(WindowAct'0')
then cntlt"0000" else cnt lt
cnt1 end if end if end process
library ieee use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity cnt_app2 is
port( clk,nclr,WindowAct in std_logic y
buffer std_logic_vector(0 to 6)) end
cnt_app2 architecture a of cnt_app2 is signal
cnt std_logic_vector(3 downto 0) begin
Cnt ??
Cnt3..0? ??
82
Timing Design Counter Application (4)
2. ???? ?? cnt3..0? ?? Y0, Y3? ?? ? ????
83
Timing Design Counter Application (5)
Y0 ???
Y3 ???
process(cnt) begin if( cnt2)
then y(0)lt'1' else y(0)lt'0' end
if end process
process(cnt) begin if( cnt10)
then y(3)lt'1' else y(3)lt'0' end
if end process
84
Timing Design Counter Application (6)
3. Y1,Y2,Y4? ????
85
Timing Design Counter Application (7)

• process(nclr,clk)
• begin
• if( nclr'0') then
• y(1)lt'0'
• elsif(clk'event and clk'0') then
• y(1)lty(0)
• end if
• end process
• y(2) lt y(0) or y(1)
• y(4) lt y(1) or y(3)

Y0? clk? falling edge? ???? ????? ??? ????Y1? ??
? ??.
Y2? Y0? Y1? OR ? ??? ? ? ??. Y2 Y0 or Y1
Y4? Y1? Y3? OR ? ??? ? ? ??. Y2 Y0 or Y1
Y2,Y4???
86
Timing Design Counter Application (8)
4. Y5,Y6? ????
87
Timing Design Counter Application (9)

• process(nclr,clk)
• begin
• if( nclr'0') then
• y(5)lt'0'
• elsif(clk'event and clk'1') then
• if(cnt2) then
• y(5)lt'1'
• elsif(cnt10) then
• y(5)lt'0'
• else
• y(5)lty(5)
• end if
• end if
• end process

Y5??? Cnt2? ? 1? ??? Cnt0? ? 0?? ???. Clk?
rising Edge??
process(nclr,clk) begin if( nclr'0')
then y(6)lt'0' elsif(clk'event and clk'0')
then if(cnt2) then y(6)lt'1' elsif(cnt
10) then y(6)lt'0' else y(6)lty(6)
end if end if end process end a
Y6??? Cnt2? ? 1? ??? Cnt0? ? 0?? ???. Clk?
Falling Edge??
88
Timing Design Result (1)
89
Timing Design Result (2)
90
Timing Design Result (3)