High-Level Synthesis for On-line Testability

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High-Level Synthesisfor On-line Testability
P. Oikonomakos and M. Zwolinski Department of
Electronics and Computer Science, University of
Southampton Hampshire SO17 1BJ UK
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On-line testing

• targets physical system failures
• detects them while system is operating
• increases reliability in several safety-critical
  applications, especially in hostile environments,
  e.g.

• flight/space electronics
• industrial/automotive electronics
• medical electronics
• deep submicron technologies

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High-level synthesis

• the designer provides an abstract specification
  of the behaviour of his conceptual design along
  with his constraints and requirements
• the synthesis tool is responsible for producing
  an equivalent structural description
• high-level synthesis offers

• fast time-to-market
• fast and efficient design space exploration
• efficient design optimisation at the highest
  level of abstraction

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• On-line testing resources will be inserted
  automatically by the tool when the designer
  requires them
• Comparing alternative testing techniques and
  choosing the most appropriate in each particular
  case will be facilitated.

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On-line testing techniques

• self-checking design
• on-line built-in self-test (BIST)
• monitoring analogue characteristics

• In this work, we focus on self-checking design.

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Self-checking design

• CUT Circuit Under Test
• The CUT is augmented according to some error
  detecting code.
• Error detecting codes include
• parity codes
• duplication codes
• several others

• Duplication codes form the basis of our
  technique.

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Duplication testing

• CUT is functionally equivalent to CUT.
• Fault-secure by nature.

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Physical vs. Algorithmic Duplication

• Physical duplication
• Operators (hardware modules) are physically
  duplicated
• Results in more than 100 hardware overhead
• Algorithmic duplication
• Operations (functions) are behaviouraly
  duplicated
• Depending on circumstances, can result in
  significant hardware savings

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Inversion Testing

• INV(CUT) is the functional inverse of CUT.

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Physical vs. Algorithmic Inversion

• Physical Inversion
• Allied to physical duplication, has no advantage
  over it, therefore it is of no interest
• Algorithmic Inversion
• Allied to algorithmic duplication
• Depending on circumstances, can result in more
  hardware savings than the algorithmic duplication
  technique

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Conclusionsand future work

• Our first experiments (using the MOODS
  High-Level Synthesis Suite) have been
  encouraging.
• We are working towards automating the on-line
  test resource insertion process, so that no
  modification of VHDL code will be required!!!
• Our system should be versatile enough to
  recognise and apply the most beneficial
  (duplication or inversion) technique for each
  module in a given design.
• Future steps include fault simulation and
  investigating methods to test the control path of
  our designs.
• Questions?