Why PGC

1
Progate Group USA Corp. Your SOC Design Turnkey
Service Partner Since in 1991
2
Contents

• Company Profile
• Business Model
• Design Capability Highlight
• Successful Stories
• Why Progate?

3
Company Highlights
4
Progate Market Position
GDS2
System Company
Fabless Company
RTL/Netlist
RTL/Netlist
SoC IP ASIC Design Service


Wafer Testing
Pkg ASE
Final Testing
5
Technology Roadmap
Q1
Q2
Q2
Q3
2000
2001
2002
1999
6
Contents

• Company Profile
• Business Model
• Design Capability Highlight
• Successful Stories
• Why Progate?

7
Service Items

• SoC Design Turnkey Service  
• Layout Service
• FPGA to Gate Array Conversion Service
• MPW (Multi-Project Wafer) Shuttle Bus Service
• IP Service
• Production Turnkey Service ( TSMC / Progate / ASE
  )

8
SOC Design Turnkey Service
Progate

• Timing Verification
• SOC Integration
• Layout
• DFT / ATPG
• Wafer/Pkg/Test
• Test Program
• Development
• Yield Rate
• Improvement
• WIP on line
• Production Turnkey

• RTL / Netlist
• Test Pattern

9
Layout Service
Progate

• RTL / Netlist

• RTL hand-off
• Netlist DRC
• IP solution
• DFT / ATPG
• Signal Integrity
• VDSM Layout
• WIP on line

GDS2
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FPGA to Gate Array Conversion
FPGA
Gate Array
CONVERT TO
PGC CONVERSION
? XILINX ? ALTERA ? ACTEL ? LATTICE ?
CPLD/PLD/EPLD ? TTLS ? ANY TYPE FPGA  
? 0.6um TGT550 series ? 0.5um HDA9000 series ?
0.35um HDA10000 series ? PIN TO PIN COMPATIBLE  
?      PACKAGE ?      TESTING
?TSMC PROCESS
?CONVERSION TIME
GATE ARRAY DELIVERY
SIGN OFF TAPE OUT
WAFER OUT
FPGA DESIGN IN
23 WEEKS
34 WEEKS
1 WEEK
 
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MPW Shuttle Bus Service
GDS2 In
Tape out
1. MPW Request 2. Quotation process 3. Agreement
/ PO In
Package Testing 7 days
Depends on Process
7 days
12
IP Service
13
Production Turnkey Service
Progate

• GDS2/Wafer
• Test Pattern

• Tape-out/Mask
• Wafer/Pkg/Test
• Testing Program/
• Tools Development
• Yield Rate
• Improvement
• Failure Analysis
• WIP on line

GDS2
14
Contents

• Company Profile
• Business Model
• Design Capability Highlight
• Successful Stories
• Why Progate?

15
Design Capability Highlight

• The most complicated design that Progate had been
  done?
• Max gate count   2.5 Million gates (0.18um)
• Highest speed 250MHZ
• Minimum CLK skew ( 80K Flip-Flop / 0.2ns )
• Max number of CLK domain   117 CLK domains
• Max Memory blocks 173 blocks
• Number of SOC integration design experiences
  4060 

16
Silicon Proven SOC Service Flow between PGC and
Customer (1)
PGC
Customer
Data Transfer
RTL Code
Preliminary Estimation
Timing / Test / Power Analysis
RTL QA ( DC-Ultra-Plus, Power Compiler, Prime
Time, Planet )
Timing / Testability / Power Estimation Report WLM
Clock Tree Planning
( Prime Time, Design Time )
Gate-level Netlist
Logic Implementation
Pre-layout Verification
Clock Tree Mode
Clock Tree Constraints
FloorPlanning
( Planet )
( DC-Ultra-Plus, TetraMAX Power Compiler )
Logic Synthesis
Optimized(Timing/Test/Power) Gate Level Netlist
Timing / Test / Power Synthesis Optimization
( DC )
Boundary constraints Timing Exceptions
Verification
( Prime Time )
STA CDC
. STA report SDF . Timing / Power / Test Driven
Constraints . Power Analysis Report
( VCS / Verilog-XL / NC-sim / VSS / Modelsim )
Power Analysis
( Design Power )
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DESIGN SERVICE FLOW BETWEEN PGC AND Customer (2)
Silicon Proven SOC Service Flow between PGC and
Customer (2)
Gate-level Netlist
Certified Verification Results (Function / Timing
/ Power)
Pre-layout Sign Off
ATPG
( TetraMAX)
Test Patterns
Timing Driven, Power Driven, Scan-Chain
Optimization, Clock-Tree Synthesis PR
( Planet, Apollo, Clockwise )
Physical Implementation and Post-layout
Verification
Clock Tree Constraints
Timing / Power / Test Driven Layout Constraints
ATPG / Netlist Modification
(TetraMAX)
( DC-Ultra-Plus, Power Compiler, Debussy,
Apollo-Saturn )
Analysis (Timing/Testability/Power) Report
Timing / Power Re-Optimization
Post-Layout Re- Optimization
Update Gate-level Netlist ATPG Patterns
RC Extraction / Layout Verification
( Start-RC, Hercules )
Boundary constraints Timing Exceptions
Verification
( Prime Time or Star-DC )
STA CDC
( VCS / Verilog-XL / NC-sim / VSS / Modelsim)
STA Report and SDF
Power Reliability Analysis
( Power Mill, Rail Mill )
Power Reliability Report
Verification Results
Post-layout Sign Off
Test Patterns
Mask Foundry
Package
Sample Testing
Good Sample Chips
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Testing Capability
(Clean Room Class 1000 )
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Contents

• Company Profile
• Business Model
• Design Capability Highlight
• Successful Stories
• Why Progate?

20
Success Stories (1)

• 0.35um 2P3M SOC chip
• Embedded 8051/DAC/ADC/PLL/I2C
• DFT, ATPG and BIST design
• Chip size 300x300 mil2
• Application Multimedia

• 0.18um 1P6M 2 Million Gate Chip
• 173 Memory instances
• DFT, ATPG and BIST design
• 133Mhz / Chip size 365365 mil2
• Application Base Station

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Successful Stories (2)

• 0.25um 1P5M 1Million Gate chip
• Low power design (save 10)
• DFT, ATPG and BIST design
• Chip size 334x334mil 2
• Fault coverage 98.5

• 0.25um 2P4M Mixed Signal chip
• Embedded PLL/ Customized block
• DFT, ATPG and BIST design
• Chip size 300x300mil 2
• Application Telecom

22
Diversified Customer Portfolio
System
IDM
Fabless
SONY Semiconductor
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Customers Applications
DVD
Digital Camera
PDA
Camcorder
Set-Top Box
Cellular Phone
MP3
TV Decoder
IP Phone
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Contents

• Company Profile
• Business Model
• Design Capability Highlight
• Successful Stories
• Why Progate?

25
Why Progate?

• More than 650 successful ASIC design experience
• ASIC one stop shopping
• Expertise in TSMCs technology
• Silicon proven SOC design flow
• Highly 1st time successful rate
• Yield rate and ASIC quality enhancement
• Faster time to market

26
Contact Information
Andrew Wu Sales Account Manager Tel 408-573
6836 Cell 408- 655 4258 E-mail
andrew_at_progate-usa.com Add 2033 Gateway Place,
Suit 500 San Jose, CA 95110 Web
www.progate-usa.com