Architectures for mobile and wireless systems

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Architectures for mobile and wireless systems

• Ese 566 Report 1
• Hui Zhang
• Preethi Karthik

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Papers Selected

• 1) Gonzales,"Micro-RISC Architectures for the
  Wireless Market", IEEE Micro, July-August 1999,
  pgs 30-37.
• 2) H. Ikeda et. al," SuperENC MPEG-2 Video
  Encoder Chip", IEEE Micro, July-August 1999, pgs
  56-65.
• 3) J. Kin,"Exploring the Diversity of Multimedia
  Systems", IEEE Transactions on VLSI, June 2001
• 4) M. Wan, Design Methodology of a low-energy
  Reconfigurable Single-Chip DSP System,J. VLSI
  Signal Processing, 2000
• 5). H. Zhang et. al,"A 1V Heterogeneous
  Reconfigurable Processor IC for Baseband Wireless
  Applications",IEEE Journal on Solid State
  Circuits, Vol. 35, Nov 2000, pgs 1697-1704.

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Introduction

• Multimedia System
• - High-performance, flexible, scalable,
  computation intensive
• - µP or DSP processor
• Wireless System
• - Low power
• - ASIC
• Multimedia System for Wireless System
• - Low power, high performance, flexibility
• - Heterogeneous reconfigurable DSP

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Introduction
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Micro-Risc Architecture for the Wireless Market

• Applications wireless handsets
• Focus low power
• Architecture 32 bit architecture
• Features low power, embedded, compiler friendly
  processor

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Micro-Risc Architecture for the Wireless Market

• Instruction set efficiency
• Special low power modes for static operation
• Power consumption for dynamic operation
• High code density
• Architecture 32-bit

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Micro-Risc Architecture for the Wireless Market

• System-level power management instructions for
  enabling external logic to disable power to some
  parts of system
• power aware instruction pipeline
• high code density creating a small executable file

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Micro-Risc Architecture for the Wireless Market

• Very less data transfer instructions and memory
  accesses (single cycle memory access)
• 16 bit instruction set
• Bus activity is reduced due to large number of
  registers
• Usage of a protocol timer which offloads
  computation intensive tasks

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Micro-Risc Architecture for the Wireless Market
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Super ENC MPEG-2 Video Encoder chip

• Applications used for encoding video signals of
  all types
• Focus high video quality
• Architecture 3 layer integrated architecture
• Hw/sw communication one software module per
  layer
• Input specification video input, bit-stream
  output
• Features low-cost, single-chip,
  high-performance, flexible, scalable

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Super ENC MPEG-2 Video Encoder chip

• Classification Data dominant
• Features Allows video encoding for different
  picture models
• Architecture 3 layer model
• Layer 1 Data buffering
• Layer 2 Video processing
• Layer 3 Process control
• independent modules except for data transfer
• scalable

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Super ENC MPEG-2 Video Encoder chip

• Hardware/Software Integration
• One software module per layer
• Rate control done by software
• Concept
• The video signal is given as an input to the
  video encoder and the output is a bitstream.
• Motion estimation and motion compensation modules
• Layer 1 Due to limited memory, data buffering is
  don
• Layer 2 The current signal is compared with the
  reference signal and checked for temporal
  redundancy removal
• Layer 3 The process control is in this layer

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Exploring the diversity of Multimedia Systems

• Characteristic Data intensive application
• Computation intensive
• Scalable
• Complex
• High performance

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Multimedia system for wireless applications

• Reconfigurable processors form a new class of
  architectures that can potentially fill the
  middle ground between flexibility and energy
  efficiency.
• They offer the advantage of combining flexibility
  and low energy by providing a direct spatial
  mapping from algorithm to architecture, hence
  reducing the control overhead typically
  associated with instruction-set processors.

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Low power reconfigurable system

• Why need flexibility and adaptability for
  wireless system?

It is a necessity in the presence of multiple and
evolving standards, and helps to increase
quality-of-service in the presence of dynamically
evolving channel conditions
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Heterogeneous Architecture Template
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Pleiades A Low Power Reconfigurable DSP
Architecture Template
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Pleiades A Low Power Reconfigurable DSP
Architecture Template
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Pleiades A Low Power Reconfigurable DSP
Architecture Template

• Design Methodology

The goal of the architectural exploration process
is to partition the application over
control-driven computation on the general-purpose
microprocessor and data-driven computing on the
clusters of satellites so that performance and
energy dissipation constraints are met. Besides
this, optimizations related to reconfigurability
have to be supported at both the architecture
design as well as compilation stage.
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Pleiades A Low Power Reconfigurable DSP
Architecture Template
Algorithm Characterization and Bottle-neck
Detection The inherent computational complexity
(counts of basic operations and memory accesses)
is a meaningful measure to identify dominant
kernels. Base on this information, the designer
can rewrite the code t o either reduce the
inherent cost of the algorithm, or extract
kernels into procedure calls. these procedure
calls are then considered for potential hardware
acceleration
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Pleiades A Low Power Reconfigurable DSP
Architecture Template
Architecture Characterizations and
Modeling Instruction-level modeling has emerged
as the preferred method for characterizing the
energy consumption of general-purpose cores. The
power-characterization of the satellite modules
is somewhat more complex. Moving components from
soft to hardware are only worthwhile when
resulting in substantial improvements, making
some inaccuracy acceptable.
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Pleiades A Low Power Reconfigurable DSP
Architecture Template
Reconfigurable Interconnect Architecture
Evaluation 1. Multi-Bus. The advantages are full
connection flexibility and simple implementation,
the disadvantages are a large area overhead and
high energy consumption. 2. Irregular Mesh the
advantage is low-cost connections between local
modules the disadvantages are high energy and
delay cost for long connections between distant
modules 3. Hierarchical Mesh provide
energy-efficient and high-performance
inter-cluster connections.
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Pleiades A Low Power Reconfigurable DSP
Architecture Template
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A 1V Heterogeneous Reconfigurable Processor IC
for Baseband Wireless Applications
Maia CELP-based speech coder for wireless
devices
1 microprocessor (embeded ARM8), 21 Satellites
processors 2 MAC, 2 ALU, 8 address generators, 8
embedded memories, 1 embedded low-energy FPGA.
two-level hierarchical mesh-structured
reconfigurable interconnect network
By partitioning the algorithm across processor
and Pleiades satellites, more than an order of
magnitude of improvement in energy efficiency is
achieved.
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Conclusions

• In the various systems we have discussed we see
  the importance of the matching of the
  methodology and architectural configuration to
  meet the system requirements.
• Multimedia systems demand flexibility and
  scalability of systems besides high performance.
• Wireless systems have to be low power while
  performing as earlier.
• Wireless multimedia systems are more demanding
  because of the conflicting requirements.