Reliability Analysis of the Aeroflex ViaLink

1
Reliability Analysis of the Aeroflex ViaLink FPGA

• MAPLD International Conference
• September 8, 2005
• Session D Reliability
• Ronald Lake
• Aeroflex Colorado Springs
• www.aeroflex.com/radhardFPGA

2
Agenda

• Background
• Aeroflex begins QML-Q / QML-V Qualification of
  RadHard Eclipse FPGA
• Original approach followed MIL-PRF-38535
  standards
• Approach outlined in previously published papers
• Then the world changed (Industry Tiger Team,
  Aerospace Corp., NASA GSFC, etc.)
• New Approach
• November 2004 Aeroflex received Aerospace
  Requirements for FPGAs in Space
• Aeroflex adopts enhanced MIL-PRF-38535 QML
  Qualification with Aerospace Corporation
  guidelines
• Un-programmed burn-in
• Operating life test (HTOL / LTOL)
• Current Status
• Aeroflex completes QML-Q / QML-V qualification
  August 2005
• Standard Microcircuit Drawing (SMD) 5962R04229
• Aeroflex announces QML results September 2005
  (MAPLD)
• Aeroflex ships first Rad-Assured QML materials
  September 2005

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QML Qualification Compliance Matrix
Aeroflex vs. Aerospace Corp. Guidance
4
Aerospace Evaluation

• Structural Evaluation
• Using focused ion beam techniques
• Output 3 dimension model (colorized)
• Follow-on evaluations
• Effect on adjacent ViaLinks
• Lot to Lot variation
• Via Links vs Programming
• Spatial Wafer Evaluation (center to edge)
• Lot to Lot variations
• Failed ViaLink (if possible)

5
Un-programmed ViaLink Cross Section
Figure removed until Proprietary issues are
resolve. This was a late arriving paper and I
apologize for this, I was too nice and will fix
that for MAPLD 2006. -- rk
6
Reliability Design for ViaLink Operating Life

• Goal Create worst case design for ViaLink stress
• Adhere to NASA OLD guidelines for reliability
  test vehicles for fuse based FPGAs
• Design
• Use all FPGA logic, memory and I/O resources
• Use all wiring types, with associated ViaLinks
• Force high fan-out structures for flip flops and
  logic
• Maximize current density through ViaLinks
• Manually fix placement to force use of long wires
  and worst case ViaLinks
• Use dedicated and global clocks for synchronous
  logic
• Synchronize reset to insure initialization
  conditions
• Create long combinatorial and synchronous chains
  for AC delay measurements

7
Life Test Environment for RadHard Eclipse

• Goal Subject RadHard Eclipse to real world
  environment during life test to stress ViaLinks
• Life test conditions
• Do not de-couple or terminate I/O signals
• Allow voltage spikes on inputs
• Allow noise on I/O and within wiring array of
  ViaLinks
• Evaluate multiple power sequencing conditions
  
• Use extended times in stress chambers
• Closely monitor power supplies

8
Test Environment for Characterization

• Goal Create repeatable and accurate test
  environment for measurement of RadHard Eclipse
  ViaLink characteristics
• Test Conditions
• Use Teradyne Tiger tester for accurate
  measurements of quiescent current and propagation
  delay
• Test all temperature conditions -55ºC, 25ºC and
  125ºC
• Test all voltage conditions 2.3V core
  and 3.0V I/O 2.5V core and 3.3V I/O
  2.7V core and 3.6V I/O
• Use control units to verify test
  environment does not change
  between stress read points
• Review all test results prior to next
  stress, comparing worst case deltas
  to means

9
Un-programmed burn-in

• Applied to 100 of un-programmed units passing
  manufacturing stress
• Standard step in Aeroflex QML manufacturing flow
• 240 hrs of 125C burn-in at maximum operating
  conditions (Vcc2.7V, Vccio3.6V)
• FPGAs dynamically stimulated during burn-in
• After burn-in devices tested for quiescent
  current (Icc, Iccio) and un-programmed electrical
  test (3 temperature, min/typ/max voltage)
• Percent defective allowable (PDA) lt5

10
Operating Life AC Deltas

• LTOL 77 test units 3 control
• No ViaLink failures at 1000 Hrs stress
• lt3 change in propagation delay
• HTOL 77 test units 3 control
• No ViaLink failures at 1000 Hrs stress
• lt10 change in propagation delay
• Delay deltas calculated for all voltage
  temperature combinations

Reliability Design Feature Details Clock
Synchronous Scan Chains 560 bit fast data quadrant
Two 360 bit Chains - high fan-out (16), fast data dedicated
Two 225 bit Chain - high fan-out (16), fast data global
SRAM 3072x18 quadrant
Register File 64x8 quadrant
Registered I/O Buffers global
Combinatorial Chains NAND w/ fanout 16
251 bit NAND w/ placement, 251 bit NAND, autoplace
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Co60 AC Deltas

• Deltas calculated at room temperature for all
  voltage combinations
• lt5 change in delay at 100 krad(Si)
• lt15 change in delay at 300 krad(Si)
• Irradiated at 1 rad(Si)/sec
• Propagation delays stay within simulation limits

Reliability Design Feature Details Clock
Synchronous Scan Chains 560 bit fast data quadrant
Two 360 bit Chains - high fan-out (16), fast data dedicated
Two 225 bit Chain - high fan-out (16), fast data global
SRAM 3072x18 quadrant
Register File 64x8 quadrant
Registered I/O Buffers global
Combinatorial Chains NAND w/ fanout 16
251 bit NAND w/ placement, 251 bit NAND, autoplace
12
Radiation Testing
Single Event Effects
Total Ionizing Dose
Dose Rate
13
Timing Characterization
QuickLogic Timing Release Flow
Oscillator Design (34 types)
Initial Data Collection
Re-Simulate Oscillator Designs
Silicon Vs Simulation
Spde Release
Timing Generation

• Pre Release Data
• Aeroflex

• Aeroflex

• QuickLogic

• Aeroflex

• Aeroflex

• QuickLogic

Verification Loop

• Current Status
• Aeroflex speed grade -5 primitive library
  provides gt10 guard band vs. silicon for
  combinatorial and most synchronous delays
• Margins maintained for material after TID of
  300krads (Si)
• Some exceptions exist due to Aeroflex removal of
  charge pump on FPGA
• Delay library undergoing updates for 4Q2005
  release

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Summary

• Aeroflex Colorado Springs has embraced the
  Aerospace Corporations guidelines to enhance the
  QML qualification flow
• Burn-in analysis demonstrates lt3 defective
  after 3 temperature testing (QML lot acceptance
  PDAlt5)
• Worst case conditions used for ViaLink operating
  life test
• LTOL delay analysis demonstrates lt3 change in
  propagation delay after 1000 Hrs of stress
• HTOL delay analysis demonstrates lt10 change in
  propagation delay after 1000 Hrs of stress
• TID delay analysis demonstrates lt5 change in
  propagation delay at 100krad and lt12 change at
  300krad
• ViaLink structural and elemental analysis
  underway with Aerospace Corporation
• RadHard Eclipse FPGA qualified as Rad-Assured QML
  Q/V