A System Designers View on SoC Communication Architectures

1
A System Designers View on SoC Communication
Architectures

• Prof. D. Stroobandt
• Dr. J. Dambre
• Ghent University, Belgium
• dstr_at_elis.UGent.be
• http//www.elis.UGent.be/dstr/

2
Outline

• Interconnect from a system designers perspective
• Some optical interconnect solutions
• Research methodologies for evaluating
  interconnect alternatives

3
The System-on-Chip (SoC) revolution

• IP-reuse
• Platform-based design
• Network-on-Chip (NoC)
• On-chip interconnect properties affect system
  design!

Yesterday and Today
ASIC design
System-Board Integration
Today and Tomorrow
Design of IP blocks
System-Chip Integration
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Interconnects dominate

• Communication requirements increase

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Interconnects dominate

• Relative communication delay increases
• Interconnects do not scale as components

gates wires
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Interconnects dominate
Source IBM
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Interconnect from a system designers
perspective matching requirements with
available and future technologies
?
System-level specifications
Required interconnect properties
?
Technological interconnect/ component properties
Impact on system performance
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Interconnect from a system designers
perspective system-level requirements

• system functionality
• system performance system tasks must be
  performed within given time span
• system cost overall power budget, production
  cost, design cost, ...
• other system properties reliability, working
  conditions, life span, ...

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Interconnect from a technology designers
perspective

• Technology development for individual components,
  e.g.
• Standard cell library design
• Low-k dielectrics research
• Copper and other materials
• Physical properties of (combinations of)
  components, e.g.
• efficiency
• throughput
• crosstalk
• power budget

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Interconnect from a system designers
perspective matching requirements with
available and future technologies
?
System-level specifications
Required interconnect properties
Very wide gap to bridge
?
Technological interconnect/ component properties
Impact on system performance
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Interconnect from a system designers
perspective matching requirements with
available and future technologies
System-level communication specifications
System-level communication specifications
Required properties of communication architecture
Communication architecture
Required link properties
Impact on system performance
Technological link properties
Impact on performance of communication
architecture
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System-level interconnect requirements

• raw demand communicating parallel processing
  units (transistors up to networked computers)
• performance communication must be realized
  within certain time
• cost of interconnect overall power budget,
  production cost, design cost, ...
• other interconnect properties reliability,
  working conditions, life span, ...
• Not all hard requirements trade-offs can/must be
  made!!

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Interconnect demand

• network size (number of processing units)

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Interconnect demand

• network size (number of processing units)

• point-to-point vs. point-to-multipoint

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Interconnect demand

• network size (number of processing units)

• point-to-point vs. point-to-multipoint

• link multiplicity

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Interconnect demand

• network size (number of processing units)

• point-to-point vs. point-to-multipoint

• link multiplicity

• static vs. dynamic demand

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Interconnect from a system designers
perspective matching requirements with
available and future technologies
System-level communication specifications
Required properties of communication architecture
Communication architecture
Required link properties
Impact on system performance
Technological link properties
Impact on performance of communication
architecture
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The communication architecture(or
interconnection network)
mapping
communication architecture
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The communication architecture(or
interconnection network)
communication architecture
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The communication architecture(or
interconnection network)
ring
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The communication architecture(or
interconnection network)
mesh
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The communication architecture(or
interconnection network)
bus
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The communication architecture(or
interconnection network)
dedicated
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The communication architecture(or
interconnection network)

• architecture type
• static vs. reconfigurable
• reconfiguration time
• latency / throughput
• redundancy
• etc.

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Interconnect from a system designers
perspective matching requirements with
available and future technologies
System-level communication specifications
Required properties of communication architecture
Communication architecture
Required link properties
Impact on system performance
Technological link properties
Impact on performance of communication
architecture
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The communication channel or link

• A link is defined from output of processing unit
  to input of processing unit
• Restrictions of electrical interconnect, e.g.
• throughput and density limitations,
• signal integrity problems (noise, coupling, ...),
• etc. ...
• have been driving force behind research into
  alternative interconnect technologies
• optical interconnect
• RF interconnect
• other, more exotic alternatives

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The optical link
detector
pathway (free space, fiber, wave guide)
receiver
driver
source/modulator

• A link is defined from electrical out to
  electrical in

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Outline

• Interconnect from a system designers perspective
• Some optical interconnect solutions
• Research methodologies for evaluating
  interconnect alternatives

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Important optical link properties

• Behavioral
• clocking behavior synchronous, asynchronous or
  something in between
• timing parameters latency, skew,
• power dissipation, speed-power product
• aggregate bit rate, error rate
• Topological point-to-point vs. broadcast or bus
  parallelism (i.e., number of parallel channels)
• Metrical distance covered required density

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The interconnect space examples
Behavior
globally synchronous
Link between L2-cacheand main memory
locally synchronous
asynchronous
single, P-P
intra-chip
multiple, P-P
Parallel Datacom link
MCM
single, SMP
board level
multiple, SMP
backplane
cabinet
Metrics
Topology
Clock distribution tree
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Interconnect contextsTelecom is not Datacom
Link is not Short-haul Interconnect
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Interconnect contextsTelecom is not Datacom
Link is not Short-haul Interconnect

• The right interconnect properties strongly
  depend on the systems interconnect requirements
• (Optical) interconnect solutions must be tailored
  to the systems interconnect context

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Where are the biggest questions?Optical
interconnect
Telecom data links
Recent and ongoing research (OIIC, IO)
Future research
IST-Project Interconnect by Optics
(http//www.intec.UGent.be/io/)
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What Could It Look Like ?

• 3-D extension of electrical on-chip interconnect
  fabric
• highly compact and densely interconnected system
• essentially 3-D routing environment, shorter
  average lengths, faster systems
• increased routability of complex designs
• Other (hierarchical) interconnect schemes could
  be envisioned

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A demonstrator system
OIIC Project (http//www.elis.UGent.be/jvc/oiic/s
ysdemo.htm)
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In-package glass sheet solution
An alternative pathway is based on waveguides in
glass sheets This pathway is directly integrated
in the PCB
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Outline

• Interconnect from a system designers perspective
• Some optical interconnect solutions
• Research methodologies for evaluating
  interconnect alternatives

38
Interconnect from a system designers
perspective matching requirements with
available and future technologies
System-level communication specifications
Required properties of communication architecture
Communication architecture
Required link properties
Impact on system performance
Technological link properties
Impact on performance of communication
architecture
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Evaluating the impact of interconnect properties
on system performance

• Within each type of system or application domain,
  individual designs and individual implementations
  differ
• ?Want to evaluate interconnect alternatives
  across this variation, i.e., make a statistical
  statement about their benefits/drawbacks

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Evaluating interconnect alternativesresearch
methodologies

• Simulation
• perform large number of experiments on
  significant number of relevant problem instances
• Statistical modeling
• combine most important statistical properties
  from communication requirements and interconnect
  performance

In the past applied to evaluate (optical and
electrical) interconnect
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Exploring interconnect alternatives in VLSI
design
Dedicated communication architectureoptimal
assignment of processing units (placement)
optimal communication path (routing)
Very large networkswith fixed topologyand
single bit links that can be point-to-multipoint
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Exploring interconnect alternatives in VLSI
design
Links can be implemented in a single or in
multiple technological variants Interconnect
properties are strongly dependent on distance
between connected blocks (wire length)
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Simulation probing the effect of short-haul
optical interconnects (OI) in FPGAs

• Perform a large number of implementation
  experiments
• Onto a variety of multi-FPGA configurations
• Using public-domain benchmarks (ISPD98)
• Estimate maximum clock frequency of synchronous
  circuits

OI
J.Dambre, H. Van Marck, and J. Van Campenhout,
Proc . Photonic Interconnect 99
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Result increase in operation speed possible with
low-latency optical interconnect

• 3-D interconnect leads to performance gains if
  optical link latency is small enough
• Gains biggest for large and complex circuits

Impact of circuit interconnect complexity for
benchmarks apex4 (non-complex) and i10
(complex)
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Early performance evaluation needed
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Early performance evaluation needed
Fast estimates as indication of whether or not a
proposed solution is far from or near to the
Pareto front. If it is far away discard. If it
is close gradually improve estimation accuracy.
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Interconnect-centric HW design
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Statistical modelingInterconnect prediction for
VLSI design
Predict length distribution of interconnections
in optimized placement
Statistically characterize interconnect
requirements
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Interconnect prediction for VLSI design
Wire length distribution
Probabilistic wire length variability across
multiple layout runs Not accurate lengths of
individual wires for particular run!
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Components of thePhysical Design Step
Circuit
Architecture
Layout generation
Layout
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The Three Basic Models
Circuit model
Logic block
Net
Terminal / pin
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Interconnect prediction details

• Suggested
• reading

D. Stroobandt. A Priori Wire Length Estimates
for Digital Design. Kluwer Academic
Publishers, 2001, 324 pages
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Prediction of interconnect lengths in VLSI design
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Recent work on wire lengthdistribution
estimations
Correlation 0.800 -gt 0.999
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Recent work on wire lengthdistribution
estimations
Correlation 0.986 Average error 6.57
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Interconnect prediction for VLSI design
Wire length distribution

• Interconnect lengths affect
• cost
• power dissipation
• yield
• performance (clock cycle)
• etc. ...

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Prediction of minimal clock cycle in synchronous
digital systems
Wire length distribution
Distribution of gate and wire delays
Distribution and expected valueof minimal clock
cycle
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Prediction of achievable clock cycle in VLSI
design
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Technology Extrapolation

• Extrapolation
• to future
• systems
• Roadmaps.
• GTX et al.

A. Caldwell et al. GTX The MARCO GSRC
Technology Extrapolation System. IEEE/ACM DAC,
pp. 693-698, 2000
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Interconnect prediction forthree-dimensional
systems
Wire length distribution for 3D system
Wire length distribution
Technology and design parameters

• Additional parameter
• Relative cost of 3D interconnection

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Three-dimensional Chips

• Different asymptotic average wire length

Two-dimensional
Three-dimensional
J. Van Campenhout, H. Van Marck, J. Depreitere,
J. Dambre, Optoelectronic FPGAs IEEE J. Sel.
Topics in Quant. Electr. (5)2, 1999, pp. 306 --
315
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Three-dimensional Chips

• Wire length distribution differs significantly

J. Van Campenhout, H. Van Marck, J. Depreitere,
J. Dambre,Optoelectronic FPGAs IEEE J. Sel.
Topics in Quant. Electr. (5)2, 1999, pp. 306 --
315
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Effect of Anisotropy

• Benefits are lower if anisotropy is higher

J. Van Campenhout, H. Van Marck, J. Depreitere,
J. Dambre,Optoelectronic FPGAs IEEE J. Sel.
Topics in Quant. Electr. (5)2, 1999, pp. 306 --
315
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Prediction of routing resources (area)
Wire length distribution
Layer assignment and effect of vias
Estimation of required routing resources
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Models of achievable routing

• Wire length estimation models (Donath, )
• Actual placement information

• Required versus available resources

• Required versus available resources

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Models of achievable routing

• Required versus available resources

• Limited by routing efficiency, power/ground nets
  and via impact

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A Typical Layer Assignment Example
Tier type 2
Tier type 1
Tier type 0
Wire width (mm)
Delay (ps)
0
2
4
0
0
2
2
4
Number of repeaters
Wire length (mm)
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Optimal Layer Stack Monotonic?
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Possible Applications of Layer Assignment Models

• A priori yield estimates (design for
  manufacturability)
• Interconnect functional yield model for cuts and
  bridges
• Relation to wire length distribution
• Total or average power estimates
• Total area estimates
• Prediction of wiring demands in FPGAs

P. Christie and J. Pineda de Gyvez. Pre-layout
prediction of interconnect manufacturability.
Proc. Intl. Workshop on System-Level interconnect
Prediction, pages 125 131, March 2001. M.
Hutton. Interconnect prediction for programmable
logic devices. Proc. Intl. Workshop on
System-Level interconnect Prediction, pages 125
131, March 2001.
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Interconnect prediction for Network-on-Chip
systems
Wire length distribution for NoC
Wire length distribution
Technology and design parameters

• Additional parameters
• Number and size of NoC islands
• Characteristics of the network
• Relative cost of network interconnection

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Technological properties that are most important
for system performance

• Latency and throughput
• average, dependence on network configuration and
  node assignment
• Reconfiguration time in relation to time-scale of
  communication requirement variations

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Summary

• From a system designers perspective, the
  evaluation of interconnect technologies is
  inevitably linked to an application domain and
  its interconnect requirements
• Technological properties that are most important
  for system performance are latency and throughput
• For evaluating the benefits/drawbacks of
  interconnect solutions, simulation and
  statistical modeling can be and have been used
• System-level interconnect prediction techniques
  are particularly suited to technology and
  communication architecture exploration