FFT Mapping on Mathstar

1
FFT Mapping on Mathstars FPOA FilterBuilder
Platform

• MathStar, Inc.
• Sept 2004

2
Agenda

• MathStar FPOA Architecture
• Program Development Model
• 1024 Complex FFT Implementation

3
Architecture Summary

• Heterogeneous Array of 16-bitSilicon Objects
• MAC, ALU, Truth Tables, Register File,CRC, CAM,
  Block RAM
• Single Clock Cycle Execution for All Objects
• Homogeneous 2-Layer Interconnect Mesh
• Tightly Integrated Data and Control Flow
• Integrated DDR DRAM SRAM Controllers
• High Speed I/O at Device Boundaries
• SerDes, LVDS, HSTL, LVCMOS

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Silicon Objects

• ALU-Truth Table-Data Router
• 8 instructions/ALU
• 4 4-term Boolean Function
• 16-bit Single Cycle MAC with 40-bit ACC
• 64 20-bit word Register File
• Dual-Port/FIFO/Sequencing
• Content Addressable Memory
• State Machine/Lookup Table
• Internal SRAM Block
• External DDRII/RLDRAM Controller
• 800MHz DDR LVDS/250MHz HSTL
• RapidIO,HyperTransport,SPI4
• 1 to 4.25GHz 1x 2x or 4x SerDes
• PCI-Express,RapidIO,XAUI,Fibre Channel, GigE
• 8B/10B 64/66 codec

5
Communication Architecture

• Each 21-Bit Link consists of16 data bits, 1
  valid bit, 4 control bits
• Nearest Neighbor Links
• Range of 1 Object (N/E/S/W, diagonals)
• No Latency Dataflow to Nearest Neighbors or
  Intra-Object
• Party Line Links
• Extend 3 Objects in One More Clock
  Cycle(25-Object Neighborhood)
• Add Clock Cycles for Data Alignment
• Add Clock Cycles to Send Data Across Chip

6
Conceptual FPOA Layout
Matrix ofSilicon Objects
ALU
RF
MAC
LVDS
iRAM
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NoGatesTM FPOA Design Flow

• Hardware Accurate Silicon ObjectModels
• Timing Accurate Connection Models for Nearest
  Neighbor and Party Line Links
• No RTL Synthesis
• No Physical Timing Closure

Summit Visual EliteCapture Design - Objects,
Connections, BehaviorFunctional Simulation with
TimingCosimulate with Verilog, VHDL, C Models
and/or Processor ISS with Firmware
MathStar OHDL
Back Annotation
MathStar COASTTMFloorplan and Assign SO
CellsConnect SO Cells
Bitstream via Parallel or JTAG
MAP File
MathStar Object CompilerTMGenerate FPOA Load
Image
JTAG
MathStar BugSprayTMIn-Circuit Verification
Debug
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Summit Visual Elite

• SystemC, C/C, VHDL,Verilog, Cosimulation
• FastC SystemC Simulator
• Multiple Abstraction Levels
• Matlab, SPW C Models
• Behavioral Models
• Detailed RTL Models
• Interactive Debug withCause and Effect Tracking
• Integration with Data Management
• Integration with AllLeading HDL Simulators
• Unlimited Hierarchy
• Block Diagrams, State Machines, Flow Diagrams,
  Truth Tables

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Mathstar COASTTM

• Drag-n-drop designobjects to physicalarray
  object sites
• Connect objects,memories, I/O cells
• Resolve any cycletiming violations
• Export MAP filewith layout data

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Radix-2 Butterfly
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Silicon Object Mapping