68HC11 Analog I/O

1
68HC11 Analog I/O

• Chapter 12

2
Analog to Digital Converter (ADC)

• What is it?
• Converts an analog voltage level to a digital
  output.
• Dout F(Vin)

3
Analog to Digital Converters

• Terminology
• Full Scale Voltage VFSVH-VL
• Difference between maximum and minimum voltage
  levels
• Bits (N) Number of bits in the digital output
• Resolution (LSB) smallest quantizing step size
• LSB Vfs/2N
• Conversion time time needed for one conversion
• Quantization error Voltage error between
  digital output and analog input.
• The maximum error is 1 LSB

4
Analog to Digital ConvertersIn General

• Given VFS, N bits
• LSB VFS/(2N)
• Digital Output Dout
• Analog Output Vout
• Vout DoutLSB Dout VFS/2N
• Quantization Error Vin - Vout

5
Analog to Digital ConvertersExample

• Given VFS5V, N2 bit
• What is the bit resolution (LSB) and the transfer
  curve
• Answer
• LSB 5/(22) 1.25V
• 0.000V lt Vin lt 1.25V ? Dout 00
• 1.25V lt Vin lt 2.50V ? Dout 01
• 2.50V lt Vin lt 3.75V ? Dout 10
• 3.75V lt Vin lt 5.000V ? Dout 11

6
2-bit Analog to Digital Converter Voltage
Transfer Curve
Dout
Vin, V
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Analog to Digital ConvertersExample

• Given VFS5V, N8 bits
• What is Dout (in hex) for Vin2.35V
• Answer
• LSB 5/(28) 0.0195V 19.5mV
• 2N 256
• Dout INT(2.35V/19.5mV)12078

8
Analog to Digital ConvertersExample

• Given VFS5V, N8 bits, Dout78
• What is the quantization error (in mV) if
  Vin2.35V
• Answer
• LSB 5/(28) 0.0195V 19.5mV
• Vout DoutLSB 12019.5mV2.34V
• QE Vout Vin 2.35V-2.34V 10mV

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68HC11 A/D Converter
8-bit resolution (256 bit levels) 8 channels
Port E
10
Port E

• 8-bit
• Address 100A
• Multi-Function
• Digital Input Port
• Analog Input Port (Built-in A/D)

11
Port E - 100A Data Register

I
I
I
I
I
I
I
I
Bits
OOutput I Input BBidirectional
12
Using the 68HC11 A/D Converter

• Power-up the A/D System
• Configure the A/D conversion system
• Two modes
• Single channel scan
• Continuous channel scan
• Channel control
• Conversion on a single channel
• Conversion on four channels
• Start the A/D conversion
• Poll the conversion completion flag (CCF)
• Read the result
• Save the result

13
Reading the Results

• Load the ADC result from the
• ADC Input Registers
• ADR1 1031
• ADR2 1032
• ADR3 1033
• ADR4 1034

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Power the A/D Converter
Option Register 1039 System Configuration
Options
CR1
DLY
N/A
CME
IRQE
CSEL
ADPU
CR2
Bits
ADPU A/D Power-up 0 A/D not
powered up 1 A/D powered up (need
at least 100uS for process to stabilize)
CSEL Clock select 0 Use
external clock (E-clock) for power up (default)
1 Use internal clock for power up
CB 11000000
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Configure the ADCA/D Control/Status Register
ADCTL Register 1030 A/D Control/Status
Register
CB
MULT
CC
CD
SCAN
N/A
CCF
CA
Bits
SCAN Continuous Scan Control 0
One cycle of four conversions each time ADCTL is
written 1 Continuous conversions
MULT Multiple Channel/Single Channel Control
0 perform four consecutive
conversions on a single channel 1
perform four conversions on four channels
consecutively
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A/D Control/Status Register Single Channel Mode
ADCTL Register 1030 A/D Control/Status
Register
CB
MULT
CC
CD
SCAN
N/A
CCF
CA
Bits
CD,CC,CB,CA Channel Conversion Select Bits

Mult0
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A/D Control/Status Register Multiple Channel Mode
ADCTL Register 1030 A/D Control/Status
Register
CB
MULT
CC
CD
SCAN
N/A
CCF
CA
Bits
CD,CC,CB,CA Channel Conversion Select Bits

Mult1
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A/D Control/Status RegisterConversion Completion
Flag
ADCTL Register 1030 A/D Control/Status
Register
CB
MULT
CC
CD
SCAN
N/A
CCF
CA
Bits
CCF A/D Conversion Complete Flag 0
Conversion not complete 1
Conversion complete. Set when all four A/D
result registers contain
valid conversions
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Project Pseudo-Code

• Power ADC using Internal Clock
• Option (1039) ? 11000000
• Delay Loop
• N10
• For I 1 to N
• Next I
• Configure ADC for
• Single channel, single scan, PE0
• Set scan0,mult0, Cd,Cc,Cb,Ca to 0000
• ADCTL ? 00000000 This starts conversion

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Project Pseudo-Code

• Wait for CCF Flag
• Repeat
• Until CCF1
• Read Result
• A ? ADR1 (1031)
• Save Result
• Dout ? A

21
TPS Quiz
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Initialization Examples

• Single channel, single scan
• Set scan0,mult0
• Set Cd,Cc,Cb,Ca to select channel
• Single channel, continuous scan
• Set scan1,mult0
• Set Cd,Cc,Cb,Ca to select channel

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Initialization Examples

• Multiple channel, single scan
• Set scan0,mult1
• Set Cd,Cc,Cb,Ca to select channel pair
• Either PE0-PE3 or PE4-PE7
• Multiple channel, continuous scan
• Set scan1,mult1
• Set Cd,Cc,Cb,Ca to select channel pair
• Either PE0-PE3 or PE4-PE7

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Pseudo-codeMulti-Channel Mode68HC11 A/D
Converter

• Initialize A/D conversion system
• Power A/D system
• Enable A/D system This starts A/D conv.
• Repeat
• Until CCF1
• For n 1 to 4
• A ? ADR(n) Read ADC register n
• Out(n) ? A Save conversion
• Next n

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A/D Subroutine

• Define Symbols
• Assume standard equates
• OPTION EQU 1039
• ADCTL EQU 1030
• ADR1 EQU 1031
• ADPU EQU 11000000
• ADC EQU 00010100 Single scan-multi
  channel
• 
  PE4-PE7
• CCF EQU 10000000 CCF
• Delay EQU 1010 this is the delay
• N EQU 04

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A/D Subroutine

• Initialize the Interface
• X contains the address of the output
  string
• B contains the number of values to
  collect
• Org Program
• Start LDY Option Load address of A/D option
  register
• BSET 0,Y ADPU This power ups the
  A/D
• LDAA Delay
• Loop DECA
• BNE Loop This delay allows the A/D
  to power up
• LDAA PE0 This are the bits to
  configure the ADCTL
• STAA ADCTL Configure ADCTL and
  start conversion

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A/D Subroutine

• LDY ADCTL This is the address of
  the ADCTL
• L0 BRCLR 0,Y CCF L0 Stay here until CCF
  is set
• LDAB N
• L1 LDY ADR1
• LDX OUT
• LDAA 0,Y This will load the
  first conversion
• STAA 0,X Save this
  conversion
• INX Point to next
  character
• INY
• DECB
• BNE L1
• RTS Return from
  subroutine
• ORG Data
• OUT RMB 4

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Maximum Sampling Rate

• Nyquist Theorem Must sample at twice the
  maximum frequency of the input signal to
  reconstruct the signal from the samples.
• 68HC11 Conversion time
• 32 clock cycles 32Tc
• Maximum signal period 1/(2Fmax)
• 32Tc 1/2Fmax ? Fmax 1/(64Tc)
• Given Fclk2Mhz ? Tc 0.5uS?
• Fmax31.5KHz

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Aperture Time

• The amount of time needed by ADC to sample the
  analog input is known as the aperture time.
  In the 68HC11, 12 cycles are needed to convert
  Vin.
• If the input signal changes considerable during
  the sample, we will see Aperture Jitter, signal
  noise, or signal error due to the uncertainty
  of the input signal.

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TPS Quiz