Exam Review Lecture EECE259

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Exam Review LectureEECE259

• Dept of ECE, Univ. of British Columbia
• Professor Guy Lemieux
• April 22, 2005

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Overview

• Studying Guide
• Scope of midterm
• Exam-writing strategy
• Budget your time
• Beginning ? Midterm 2 Review
• Material A, B, C,
• Midterm 2 ? End Review
• Material , X, Y, Z

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General Studying Guide
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Scope of Exam

• Exam covers ALL course material
• All lectures
• All problem sets (1-5)
• Practise, practise, practise!
• Solve all problem set questions
• Attempt quizzes, midterms, more problem set
  questions from past years (old web sites are all
  online)
• Look online, in textbooks for more problems
• TEST YOUR ASSUMPTIONS Try it in Wookie!

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Exam-Writing Strategy

• Maximum Marks for Minimum Effort
• Review ALL questions
• Which is worth the most marks?
• Which is easiest for you?
• Which gives most marks for a partial solution?
• Develop Plan of Attack
• Answer EASIEST problems first

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Budget Your Time

• Develop a Time Budget
• Maximum minutes per question
• Based on mark value
• MAYBE adjust based on difficulty (ONLY IF 99.9
  SURE!!!)
• Reserve slack time at end, at least 10 of total
  time
• Use for checking solutions
• NEVER exceed your time budget for each problem
• Question finished early?
• Add to slack, NOT the next problem

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Budget Your Time

• Example
• 4 equal-weight questions, 60 minutes
• WRONG Budget 15m each ? no slack time!
• CORRECT Budget 13m each ? 8m slack time
• Question 1 takes only 7m
• Slack time grows 8m 6m 14m
• Question 2 still gets only 13m
• If not enough, revisit at END of test

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Beginning to Midterm 2 Review
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68HC11 Microcomputer

• CPU Memory I/O
• CPU
• ALU add, sub, logic, mul, div
• 8-bit Registers AccA, AccB, CCR
• 16-bit Registers AccD A,B, IX, IY, SP, PC
• Control Unit
• Internal Finite State Machine (FSM)

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68HC11 Microcomputer Memory

• Memory
• Stores binary numbers
• Operate on 1 byte at a time
• 16-bit address, 8-bit data
• Read data ? Memoryaddr
• Write Memoryaddr ? data

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Binary Hexadecimal Numbers

• Binary 1011 0011
• Bits are powers of 2 128, 64, 32, 16, 8, 4, 2, 1
• 128 32 16 2 1 179
• MSB ... LSB
• Hexadecimal
• Groups of 4 bits ? one hexadecimal digit
• B3

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Memorize!

• 1 01 20
• 2 02 21
• 4 04 22
• 8 08 23
• 16 10 24
• 32 20 25
• 64 40 26
• 128 80 27
• 256 100 28
• 1024 400 210
• 4096 1000 212
• 8192 2000 213
• 16384 4000 214
• 32768 8000 215
• 65536 FFFF1 216

• 0 0000 00
• 1 0001 01
• 2 0010 02
• 3 0011 03
• 4 0100 04
• 5 0101 05
• 6 0110 06
• 7 0111 07
• 8 1000 08
• 9 1001 09
• 10 1010 0A
• 11 1011 0B
• 12 1100 0C
• 13 1101 0D
• 14 1110 0E
• 15 1111 0F

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Twos Complement Binary Numbers

• Unsigned numbers
• 8-bit value, 16-bit value interpreted directly
• Signed numbers
• Twos complement format
• MSB1 means value is negative
• To convert to positive invert all bits, add 1
• To convert to negative invert all bits, add 1
• Reversible!

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Twos Complement Arithmetic

• Add/Subtract
• IDENTICAL RESULT for SIGNED and UNSIGNED
• V FLAG set assuming operands are SIGNED
• C FLAG set assuming operands are UNSIGNED
• SIGNED inspect V (overflow) flag
• -128 1 -127 ? ok, no overflow
• -128 -1 -129 ? V1, cannot represent in 8
  bits
• 127 1 128 ? V1, cannot represent in 8 bits
• UNSIGNED inspect C (carry) flag
• 127 1 128 ? ok, no carry-out
• 255 1 256 ? C1, cannot represent in 8 bits

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Twos Complement Arithmetic

• Add/Subtract with different data widths
• Sign-extend narrow data by copying sign bit
• Perform add/subtract at widest width
• Multiply
• SIGNED and UNSIGNED are DIFFERENT!
• Not the same as Add/Sub
• CPU treats MUL as UNSIGNED

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Data Types in Binary

• Binary numbers
• Stored in memory
• Really just a bag of bits
• Meaning how to interpret a bag of bits?
• Depends on data type associated with the bits
• Many data types
• Signed 8-bit number
• Unsigned 16-bit number
• 8-bit ASCII code (character)
• CPU instruction (8-bits, 16-bits, 8-bits 16-bit
  extended, etc)
• 8-bit grayscale pixel value of X-ray image
  (average brightness at one fixed point)
• 8-bit red, 8-bit green, 8-bit blue, pixel value
  of colour image

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Data Types in Binary

• Key point
• Data Type determined by You (Programmer)
• A bag of bits can mean many things
• Your program treats each bag of bits differently
• Some bags are CPU instructions
• Some bags are 8-bit signed values
• etc
• The CPU runs the CPU instructions
• The CPU reads writes data according to your
  instructions
• You choose instructions (eg, signed vs unsigned)

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Executing 68HC11 Instructions

• CPU exectutes one instruction at a time
• PC hold address of current/next instruction
• Each instruction can be 1 or more bytes
• IndexY instructions have extra PREFIX byte
• Fastest execution one byte per clock cycle
• Some instructions access memory additional
  clock cycles

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Addressing Modes 1

• Inherent (no operand, operates directly on
  register)
• ABA, INCA, CLRA
• Immediate (data immediately follows at next PC)
• LDAA 00, LDX C100
• Direct (memory operand in page 0 0000--00FF)
• LDAA 00F0, INC 00EB
• Extended (memory operand anywhere in
  0000--FFFF)
• LDAA C100, INC 01EB

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Addressing Modes 2

• Index X, Index Y
• Used to access arrays, tables of data
• LDAA 3,X ? memory address X3 used
• Relative (8-bit signed value relative to PC)
• Used for branch instructions
• BRA, BSR, BEQ, etc

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Addressing Effective Address

• Effective Address
• Final computed address of the operand
• For immediate, it is near the PC value
• For Direct, it is the page-0 address
• For Extended, it is the 16-bit address
• For Relative, it is PC 8-bit signed offset
• For Index X, it is IX 8-bit UNsigned offset
• For Index Y, it is IY 8-bit UNsigned offset

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Instruction Set Overview(10 pages)

• Memory Read/Write Instructions (eg LDA)
• Add/Subtract Instructions (eg, ADDA)
• Advanced Arithmetic (eg, MUL)
• Logical Bitmasking (eg, ANDA)
• Register-to-Register Transfers (eg, TBA)
• Comparisons (eg, CMPA)
• Shifting/Rotating (eg, LSLA)
• Simple/Complex Branches (eg, BRA/BGT)
• Subroutines/Interrupts/Misc (eg, JSR, RTI)
• Stack, Flag Manipulation (eg, PSHA, CLC)

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68HC11 Instructions 1

• Memory Read/Write Instructions
• CLR, CLRA, CLRB
• LDAA STAA
• LDAB STAB
• LDD load AccD STD
• LDS load stack STS
• LDX load X STX
• LDY load Y STY

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68HC11 Instructions 2

• Add/Subtract Instructions
• ABA SBA
• ABX, ABY
• ADCA, ADCB SBCA, SBCB
• ADDA, ADDB, ADDD SUBA, SUBB, SUBD
• INC, INCA, INCB DEC, DECA, DECB
• INS, INX, INY DES, DEX, DEY
• NEG, NEGA, NEGB

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68HC11 Instructions 3

• Advanced Arithmetic
• DAA ??
• MUL AccD AccA AccB (unsigned)
• IDIV IX AccD / IX, AccD gets remainder
• FDIV ??

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68HC11 Instructions 4

• Logical Bitmasking
• ANDA, ANDB
• BCLR, BSET
• COM, COMA, COMB
• EORA, EORB
• ORAA, ORAB

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68HC11 Instructions 5

• Register-to-Register Transfers
• TAB, TBA A to B, B to A
• TAP, TPA A to CCR, CCR to A
• TSX, TXS
• TSY, TYS
• XGDX, XGDY

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68HC11 Instructions 6

• Comparisons
• BITA, BITB tests (A/B Mem)
• TST, TSTA, TSTB tests (A/B 0) ie,
  compare-to-zero
• CBA
• CMPA, CMPB, CPD
• CPX, CPY

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68HC11 Instructions 7

• Shifting/Rotating
• ASLA, ASLB, ASLD
• ASR, ASRA, ASRB
• LSL, LSLA, LSLB, LSLD
• LSR, LSRA, LSRB, LSRD
• ROL, ROLA, ROLB
• ROR, RORA, RORB

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68HC11 Instructions 8

• Simple Branches
• BEQ, BNE
• BCC, BCS
• BPL, BMI
• BVC, BVS
• BRA, BRN
• BRCLR
• BRSET

• Complex Branches
• Signed Unsigned
• BLT lt BLO
• BLE lt BLS
• BGT gt BHI
• BGE gt BHS
• Jumping
• JMP

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68HC11 Instructions 9

• Subroutines
• BSR
• JSR
• RTS
• Interrupts
• WAI
• SWI
• RTI

• Misc
• STOP
• TEST

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68HC11 Instructions 10

• Stack
• PSHA, PSHB PULA, PULB
• PSHX, PSHY PULX, PULY
• Flag Manipulation
• CLC SEC
• CLV SEV
• CLI SEI

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Instruction Set Summary

• Memory Read/Write Instructions (eg LDA)
• Add/Subtract Instructions (eg, ADDA)
• Advanced Arithmetic (eg, MUL)
• Logical Bitmasking (eg, ANDA)
• Register-to-Register Transfers (eg, TBA)
• Comparisons (eg, CMPA)
• Shifting/Rotating (eg, LSLA)
• Simple/Complex Branches (eg, BRA/BGT)
• Subroutines/Interrupts/Misc (eg, JSR, RTI)
• Stack, Flag Manipulation (eg, PSHA, CLC)

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Assembly Language

• Directives
• instructions to the assembler only
• ORG, EQU
• FCB, FDB, FCC, RMB, BSZ, FILL
• Instructions
• Mnemonic short-hand for an instruction
• Use to force Immediate mode
• Automagically selects Direct mode
• Use 0,X or 0,Y for Index X or Y mode, where 0 is
  any constant number from 0 to 255

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Assembly Language

• Constants
• Decimal (default)
• Hexadecimal
• Binary
• ASCII in quotes
• Expressions
• Any constant can be replaced with an expression
• All expressions MUST evaluate into a constant
• Assembly pre-computes final value

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Assembly Language

• Labels
• Define new SYMBOL to hold 16-bit value
• SYMBOL can be a memory address
• SYMBOL can be any value using EQU
• Assembler automagically translates into 8-bit
  relative, or 8-bit value, when needed
• Can use in expressions
• Location Counter
• Internal to assembler only (not part of 68HC11)
• Tracks where next byte of machine code is
  emitted

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Assembly Language Listing
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Flowcharting
Loop

• Keep steps simple (1-5 asm instructions)

START
Subroutine(param1,param2)
BPL
Is MSB 1?
Loop
Increment X
No
STOP
Yes
Loop
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C-to-Assembly Example
Bad style to use EQU todefine memory
locations! Use FCB instead.
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Labels Constant Expressions
1002 - 1000
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Find Maximum Entry in Array
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Stacks and Subroutines

• SP Stack Pointer
• Points to free (unused) location on stack
• Push onto stack (write data to MemorySP, then
  SP--)
• Pull from stack (SP)
• JSR LABEL Subroutine
• Compute PC for next instruction
• Push PClo, Push PChi
• Return address pushed on stack
• Jump to LABEL by putting value into PC
• RTS when done
• Return address pulled from stack, put into PC

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Stacks Snakes and Ladders

• Always initialize SP
• LDS 01FF
• Always PULL what you PUSH (BALANCE!)
• JSR / PSHA / PULA / RTS
• Always PULL in reverse order of PUSHING
• PSHA, PSHB, PSHX, PULX, PULB, PULA
• Always PUSH LOW part of 16-bit number FIRST
• PSHX, PULA, PULB copies IX to AccD

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Subroutines Parameters

• Input parameters
• Can pass in register, eg AccA
• Output values
• Can pass in register, eg AccB
• Subroutines should not modify registers
• Save used-registers at top
• PSHA, PSHB, PSHX
• Restore registers at end
• PULX, PULB, PULA
• Output values in registers?
• Register must be changed, dont save it!
• Eg, JSR, PSHA, PSHX, subroutine details, PULX,
  PULA, RTS

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Even More Parameters?Stack Frames!

• Motivation Complex subroutines
• Need lots of input parameters
• Need to return lots of values
• Need local variables
• May be recursive
• Stack frame
• Defines a standard view of stack for each
  subroutine
• CALLER pushes return values (space), input params
• JSR pushes return address
• CALLEE pushes saved-regs, local variables

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Stack Frame Example
TSX instruction X ? SP1
Callee Allocated
Read param2 LDAA 9,X
Caller Allocated
Write return value2 STAB 12,X
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1D and 2D Arrays

• Ai, Array of unsigned bytes
• A starts at address B000
• Ai at location B000 i
• Arowcol, 2D array of unsigned bytes
• A starts at address B000
• Arowcol at location B000 rowNCOLS col
• NCOLS is number of columns
• col ranges 0 to NCOLS-1
• row ranges 0 to NROWS-1
• Called ROW MAJOR ORDER

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1D Arrays Generating Address Aj

• Usually use IX and IY
• Can easily access 2 arrays
• How to access 3, eg A B C
• Remember
• LDX ARRAY
• LDAA 3,X 3 must be a constant
• LDAA j,X works ONLY if j is constant (ie, EQU)
• To access ARRAYj, where j is a variable
• LDX ARRAY
• LDAB j
• ABX
• LDAA 0,X

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2D Arrays Generating Address Arowcol

• This code corrects an error in the ProblemSet
  3 Solutions
• GOAL Return address of Arowcol in IX
• PARAM A holds row lt 16
• PARAM B holds col lt 16
• PARAM IX holds address of A00
• AddrA PSHB
• PSHA
• LDAB N
• MUL assume answer lt 256 (ie N16)
• ABX
• PULA
• PULB
• ABX
• RTS

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Instruction Timing 1

• Each instruction takes 2..41 cycles
• Precisely known
• Depends on instruction addressing mode
• Clock frequency F 2MHz 1/T
• T 1 clock cycle period 0.5 ms
• Fastest instruction 2 cycles 1.0 ms

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Instruction Timing 2

• Fastest loop is 5 cycles or 2.5ms
• LOOP DECA (2 cycles)
• BNE LOOP (3 cycles)
• How to get 1.0ms resolution?
• NOP takes 1.0ms
• 2 NOPs take 2.0ms
• Use polling with timers in I/O system?

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68HC11 Microcomputer I/O

• Digital I/O
• Port A 8 bits, some in, some out
• Port B 8 bits output only
• Port C 8 bits input/output
• Port D 6 bits, serial I/O
• Analog or Digital
• Port E 8 bits, inputs
• Access ports via memory-mapped I/O
• Read and write special memory locations

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I/O Interfacing

• Unconditional I/O
• No delays, no waiting, just do it!
• LDAA PORTC,X read inputs on Port C
• STAA PORTB,X send outputs to Port B
• Delays
• Useful for slowly printing messages to humans
• Write your own delay routines
• Use input parameter to determine duration
• Eg, JSR DELAY1MS delays for AccA milliseconds

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Inputs on Port C
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Outputs on Port C
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I/O Interfacing Polling

• Polling
• Wait until I/O is in a particular state
• If polling mechanical switch
• Should de-bounce by waiting
• Wait for release to avoid rapid key repeating?
• Eg, wait while Port C bit 0 (PC0) is 1
• POLL1 BRSET PORTC,X 01 POLL1
• JSR DELAY5MS

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I/O Interfacing Interrupts

• Interrupts
• Keep CPU busy doing work
• Work is complex, difficult to add frequent
  polling
• Arrange hardware or timers to generate interrupts
• Good if interrupts are infrequent and work is
  small
• Main program can be interrupted anywhere
• Sometimes wish to DISABLE interrupts
• SEI to disable, CLI to enable
• Should disable when modifying interrupt
  configuration/settings

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I/O Interfacing Interrupts

• Interrupt Programming in 3 Easy Steps
• Create vector table entry
• Write the ISR
• Determine cause
• Clear cause
• Do work (must have SIDE EFFECT)
• RTI
• Enable interrupts
• Set device to send
• Set CPU to receive

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I/O Interfacing Interrupts

• Interrupt Service Routine
• CPU automagically saves ALL registers on stack
• CPU automagically sets I bit to mask further
  interrupts
• CANNOT rely on ANY register values being same
• Re-init IX, other needed registers
• End with RTI to restore ALL saved registers
• Main Program
• ISR is mostly transparent to main program
• ISR must have side effect, ie change state of
  machine
• Change outputs
• Alter memory values
• Main program should (eventually) react to this
  side effect
• Eg, when it next examines memory contents

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Midterm 2 to END Review
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Digital Logic Review
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NAND / NOR Gates
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Complex Gates - XOR
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Complex Gates - MUX
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Complex Gates Tristate Buffer
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Sequential Logic (with memory)DFF with Enable
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Sequential Logic (with memory)Level-sensitive
Latch
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Memory Internal Details
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Memory Size / Capacity
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Building a Computer
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Connecting Memory
Which device sends data on the Data Bus ?
CPU? RAM? ROM? Only one at a time! CPU
controls R/W andwhich device gets access.Which
device address decoding
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Simple Address Decoding
Note Need to disable ROM Data outputs
during WRITE operation (even if mistakenly
writing to ROM) Therefore R/W must control
OE Of ROM (use a NOT gate)
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Simple Address Decoding8kB EEPROM
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Simple Address Decoding32kB SRAM (4 x 8kB)
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SRAM Read Timing
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SRAM Write Timing
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68HC11 Computer
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6811 Write Timing
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6811 Read Timing
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6811 w/ External RAM (4 x 1kB)
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6811 Instruction Execution
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Executing INC 03,Y