Memory Part II

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Memory Part II
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Memory Technologies

• 2 ways to store a state electrically
• Determine if charge is present
• Determine if current will flow
• Can also be done magnetically, though in modern
  computers this is mainly used for secondary
  memory due to it being one step removed from
  electricity

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Registers

• Special purpose
• MBR, MAR, etc.
• General
• CPUs scratchpad
• Typically word size
• Implemented using D flip-flops
• Edge-triggered transition from logic 0 to 1 or
  1 to 0 is fast

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Main Memory

• Dynamic Memory (or DRAM)
• Minute electrical charges remember memory states
• Stored in capacitors
• 2 metal plates separated by electrical insulator
• Positive charge can be applied to one plate,
  causing negative in other
• Processor controls which plate receives charge.
  Charged is 1, uncharged is 0

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DRAM

• Capacitors hold charge for a few or few dozen
  milliseconds
• Motorola 1 MB SIMMs require refresh every 8msec,
  while some require only 32msec

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Writing data to DRAM

• 1.       Software, in combination with the OS,
  sends an electrical signal (a burst) along an
  address line, which is a microscopic strand of
  electrically conductive material etched into the
  chip (a trace). Each address line identifies a
  location in the chip where data can be stored.
  Which address line is activated ("goes high")
  identifies which location among the many in the
  memory chip where the data will be stored.
• 2.       The electrical pulse turns on (closes) a
  transistor that is connected to a data line at
  each memory location in the chip where data can
  be stored. Recall that the transistor is simply
  a microscopic switch.
• 3.       While the transistors are turned on, the
  software sends a burst of electricity along
  selected data lines. Each burst represents a "1"
  bit.
• 4.       When the electrical pulse reaches an
  address line where a transistor has been turned
  on, the pulse flows through the closed transistor
  and charges a capacitor. This process is
  repeated almost continually to refresh the
  capacitor's charge which otherwise would leak
  away.
• 5.       After the writing process each charged
  capacitor along the corresponding address line
  represents a "1" bit in the memory and the
  uncharged capacitors correspond to "0" bits.

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Reading data from dynamic memory

• 1.                When software wants to read
  data stored in the RAM, an electrical signal is
  sent along the address line corresponding to the
  address at which the desired data is located.
  This electrical pulse has the effect of closing
  the transistors connected to that address line.
• 2.                When the transistors are closed
  along a given address line, each capacitor which
  holds a charge (a "1" bit) will discharge through
  the circuit created by the closed transistors
  which will in turn send electrical signals along
  the corresponding data lines.
• 3.                The software recognizes which
  data lines the electrical pulses come from and
  interprets each pulse as a "1" bit and any data
  line for which no electrical pulse is detected is
  assumed to be a "0" bit. The combination of the
  1s and 0s taken from eight data lines forms a
  byte of data.

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DRAM continued

• Speed is crucial
• Fastest DRAM 45 to 50 nsec
• View memory like a spreadsheet
• Each cell has an address
• To write, you send row,column address and data is
  written
• To read, you do the same
• Addressing lines are multiplexed to keep number
  of connections small.
• RAS (Row Address Strobe) signal indicates that
  the address represents a row and the CAS (Column
  Address Strobe) indicates that the address line
  represents a column
• Multiplexing allows 12 address lines plus RAS and
  CAS signals to encode every possible memory cell
  address in a 4 MB chip
• Signal lines do not change state instantly so
  when coupled with refresh rate, represents
  primary limits of conventional chips. So other
  designs try to enhance the speed of RAM chips.

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Static Column RAM

• Redesign allows chips to read from with a single
  column without wait states
• Wait states cause microprocessor to suspend what
  is working on for a number of clock cycles to let
  memory catch up.
• These retained CAS, and then only RAS had to be
  changed.

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Microprocessor Speed and Memory Speed

• Microprocessor speeds these days are almost
  always expressed as a frequency in megahertz
  (millions of cycles per second) or gigahertz
  (billions of cycles per second). Memory chips
  are typically rated by access time which is
  expressed in nanoseconds or billionths of a
  second (10-9 seconds). The two numbers are
  reciprocals. At a speed of 1 MHz, one clock
  cycle is 1000 nanoseconds long at 8 MHz (the
  speed of the ISA bus), one clock cycle is 125
  nanoseconds long at 33 MHz (the speed of the
  PCI bus), one clock cycle is 33 nanoseconds long
  at 66 MHz (common front side bus speed), one
  clock cycle is 17 nanoseconds long and at 100
  MHz (newer front side bus speeds), one clock
  cycle is 10 nanoseconds long. A 1 GHz processor
  has a clock cycle of 1 nanosecond!

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Page-Mode RAM

• Memory controller first sends out a row,
  activating RAS
• While holding the RAS, a new address is sent
  along with CAS to indicate specific cell
• If RAS kept active, controller can then send out
  one or more additional new addresses, followed by
  CAS signals.
• Allows for rapid access to multiple cells in a
  single page of memory reduces time for memory
  accesses in same page by 25-30 nsec
• NOTE change in page requires change in row and
  column (incurring the speed penalty)

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Extended Data Out Memory (EDO RAM)

• Most popular for PCs with front side bus running
  at 66MHz
• Speed of EDO RAM eliminates need for secondary
  caches on lower end machines, but performs at
  even higher perceived speeds if cache is used
• Data kept valid until additional signal is
  received
• System does not have to wait for separate read
  cycle, but can read as fast as chip will allow
• To work properly, microprocessor must indicate
  when it has finished reading data.
• Theoretically, provides speed-up of 50-60,
  reality is 10-20
• With advent of 100MHz front side buses, EDO was
  outpaced
• EDO chips cannot be used in machines that use
  standard RAM chips.

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Burst EDO DRAM (BEDO RAM)

• Developed by Micron Technology
• Perform all read/write operations in 4-cycle
  bursts
• Pipeline nibble mode DRAM
• Uses pipeline to retrieve and send out data in a
  burst
• Contains fuse to allow access to controller
  circuit

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Synchronous DRAM (SDRAM)

• Operate in sync with host microprocessor
• Internal redesign of chip to make data available
  every clock cycle
• Uses pipeline design have multiple,
  independently operating stages
• Chip can start to access a second address before
  finishing the first
• Pipeline only extends across column addresses
  within a given page
• Operate at speeds as fast as 10 nsec
• Speedup is limited due to limits on SIMM sockets
• Requires special support and packaging can be
  larger

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Enhanced DRAM (EDRAM)

• Add small block of static cache to each chips,
  these provide processor with data while chip is
  refreshed
• Originally developed by Ramtron
• Linking the SDRAM cache with the DRAM on the same
  chip allows the use of a wide bus to connect the
  two. The Ramtron design uses a 16,384 bit wide
  bus link between the cache (256K) and the RAM.
  Filling the on-board cache requires about 35
  nanoseconds which is about seven times faster
  than filling an equivalent non-integral cache
  (which takes about 250 nanoseconds).
• (2) The Ramtron design allows the DRAM to be
  pre-charged at the same time the system makes a
  burst read from the cache. This pre-charging
  allows the DRAM to be ready for cache misses
  which in turn minimizes the overall memory access
  time. Conventional DRAM chips must perform both
  the pre-charge and an ordinary memory access
  whenever a cache miss occurs.
• (3)   The Ramtron on board cache uses a
  write-through design and direct writes to the
  main part of the chip can be made with zero wait
  states.

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Cached DRAM

• Mitsubishi Corp
• Has onboard cache memory
• 4MB with 2KB devoted to cache
• Cache and DRAM have independent address ports
• Operate in synchronous mode at 100MHz with zero
  wait states

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RAMBUS DRAM

• Revised interface between chips and rest of
  system
• Used in Itanium (IA-64) and in Nintendo 64
  systems
• 2048 byte static RAM cache linked to dynamic
  portion of chip via bus that allows an entire
  page of memory to be transferred to cache in
  single cycle (rate of 15nsec during cache hits)
• On a cache miss, it retrieves info from dynamic
  portion and transfers that page into cache
  (remember LOR)
• Does not link to host system like standard memory
  needs a special high-speed bus
• Speed of 250MHz, allows 2 bytes per clock cycle
  giving speed of 500MHz

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RAMBUS DRAM

• 3 types
• BASE RAMBUS
• 600MHz, bandwidth of 600MB/sec
• Concurrent RAMBUS
• 700 MHz (700MB/sec)
• Direct RAMBUS
• 800 MHz (800MB/sec)
• Direct is memory system of choice
• Uses RIMM (Rambus Inline Memory Module) that has
  16-bit interface
• Has its own control language to manage memory
• Drains 10 of bandwidth from peak transfer rate
  of system

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Multibank DRAM (MDRAM)

• Splits memory into banks
• Banks connected by a central data bus
• Has 32-bit interface
• MoSys Incorporated claims peak transfer rates of
  1 GB/sec

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Video RAM (Video Memory or VRAM)

• Frame buffer in which on screen image is stored
• Entire contents of the frame buffer are read
  anywhere from 44 to 75 times a second as image is
  displayed on monitor
• Allows writes while read is going on (2 access
  paths)
• True dual-ported memory simultaneous reading
  and writing
• Requires 20 more silicon than standard RAM, but
  speeds up video systems by as much as 40

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Windows RAM

• WRAM variation on dual-ported VRAM
• Developed for GUIs
• 8 M arranged on 32 bit plains
• 4 chips supply necessary memory for 1024 x 768
  resolution on 1024 by 1024 with bit depth of 32
  bits (good for TrueColor 24 bit operation)
• 256 bit data bus, multiplexed to 32 bit data with
  compatible with todays PC circuitry
• Has 2 serial data registers, four 32 bit
  registers
• Rates of around 640MB/sec
• Speedup 50

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Static Memory or SRAM

• Allows current to flow but alters path into one
  of two directions to mark the state
• Uses relays (acts as flip-flop)
• Closed is on, open is off
• Does not require refreshing, but does need
  constant flow of electricity
• Requires minimum of six transistors per bit of
  memory
• Not suitable to very dense memory arrangements
• Faster than DRAM, and more expensive
• Reserved for critical portions (like level 2
  cache memories)

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ROM

• Switches switch once and then jam
• ROM is random access memory just as RAM is.

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Mask ROM

• Information is built into chip when manufactured
• Memory forever embedded in the chip
• Not commonly used in PCs since programming of
  memory is required and changes are not easily made

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PROM (Programmable ROM)

• Falls in category of WORMs
• Like array of elements that each work like a fuse
• PROM burner provides current to blow the fuses
• Chips come with fuses intact, and then it can be
  customized by PROM burner
• Once burned, effects are permanent

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EPROM (Erasable PROM)

• Contain self-healing semiconductor
• Have clear window in center of top of the chip
• Chips erased by focusing high-intensity UV light
  through window, so care has to be used
• UV radiation can erase entire contents of a chip

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EEPROM (Electrically Erasable PROM)

• double-E PROM
• Use higher than normal voltage to erase contents
• Dont need to be removed from socket to reprogram
• Can be manipulated at byte level, so individual
  bytes can be erased without erasing entire chip
• Common for storing setup parameters for printers
  and other peripherals
• Memory survives switching power off
• Disadvantage can only be erased finite number of
  times, so not suitable for general storage within
  PC where cell may be changes few thousand times
  each second.

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Flash Memory (Flash ROM or RAM)

• Essentially same as EEPROM except voltage
  required are at levels normally found inside PC
• Flash ROM bulk-erase typically, but newer ones
  have multiple independently erasable blocks (size
  4K to 128K)
• 2 styles
• Sectored-erase flash
• Boot block
• one or more blocks are specially protected from
  normal erase operations (firmware)
• Support random reading and writing
• First generation requires PC or device to handle
  erase and write operations
• Current generations have on-board logic to handle
  operations
• For effective operation, need special OS or
  modified versions of current OS that minimize
  number of erase/reprogram cycles that the chip
  must endure in order to extend its lifetime