Super-Belle Vertexing

1
Super-Belle Vertexing

• Talk at Super B Factory Workshop Jan 20 2004
• T. Tsuboyama (KEK)

Super B factory Vertex group Please visit
http//belle.kek.jp/superb/vtx
2
Outline of this talk

• Coverage
• Angle 17ltqlt150o
• Full acceptance of Super-Belle detector.
• Radii13ltrlt150 mm.
• Inner radius? close to the 10 mm radius IP
  chamber. (?Tajima and Trabelsis talks)
• Outer radius? wherever CDC can not be operated
  due to beam background. (?Unos talk)
• Tracking capability
• Spatial resolution the better the better
• Internal tracking for small pt tracks.
• DAQ/Trigger issues (Higuchi/Itos talks)
• Occupancy lt5 even at the inner layer.
• Dead time lt10 at trigger rate of 30 kHz.
• Trigger latency
• 1st level Trigger from TRG to VTX 3 msec
• Z-Trigger generated by VTX to TRG 15 msec.
• Radiation hardness 20 Mrad.

3
Sensor configuration

• Belle acceptance 17ltqlt150o must be covered.
• Outer radius is determined by CDC 150 mm
• Inner radius is determined by beam pipe10 mm
• 5 layers for self tracking.

• Inclined sensors in Layer 4 and 5
• Reduce readout channels
• Save material budget
• Shorten the ladder length (Without slant sensors,
  length 75 cm)
• Innermost layer suffers serious beam background.
• DSSD (striplet) option ? Super-layer
• Pixel option ? covered by G. Vernar

4
Expected resolution

• Dotted lines SVD2(Reference)
• Cyan 0.2 GeV/c, green 0.5 GeV/c, blue 1.5
  GeV/c, Yellow 2 GeV/c.
• DSSD (Striplet) case
• Two layer will be useful for robustness under
  background.
• Thickness same as that of SVD2 / layer.
• 20 improvement because of the detector radius.
• Alice type hybrid-pixel case (Pixel
  size50mmx400mm)
• Pixel shape is flat therefore, two layers are
  necessary since single layer is not enough to
  achieve good resolution in X and Z.
• Material can not be ignored although sensors and
  amplifiers are thinned.
• Consequently, the improvement of the resolution
  can not be observed.
• Instead immunity to background will be better
  than DSSD case.

Impact parameter resolution (rf)
Impact parameter resolution (z)
Inner layer 2 layer DSSD
Inner layer 2 layer DSSD
5
DSSD for the innermost layer

• The inner most layer sensor has a size of
  50mm72mm/readout.
• With 50 um readout pitch and 1msec shaping time,
  the background estimation results in 200
  occupancy!
• In order to obtain lt5 occupancy, 40 times
  occupancy reduction is necessary.

5
6
DSSD for the innermost layer

• Occupancy is proportional to sensitive area
  shaping time.
• Readout chip with 50-100nsec shaping time is
  available.
• Strips area should be 4 to 5 times smaller.
• Narrower strips are not easy.
• We should shorten the strips.
• Strips can not be simply cut into 4-5 pieces
• Dead regions between groups appear.
• Assembly (wire bonding) becomes difficult.

7
Striplet design

• By arranging strips in 45 dgrees, strip length is
  shortened automatically.
• Small triangle dead region exists.
• About 7 in Layer1
• Benefits of this design are
• Strip arrangement on p-side and n-side can be
  symmetric.
• The above triangular dead region on one side is
  covered by the strips in the other side.
• Strip signal can be read out at detector edge.
  Assembly with high-density kapton circuit is
  easy.
• The scheme is applicable in any width/length
  ratio.

8
Prototype design in production
Production of an RD sensor is going on.
9
Readout with kapton flex circuits

• RD items
• Alignment between layers.
• Production yield and quality.
• Method of assembly
• Installation issue
• Number of front end chip is 4-5 times than the
  present SVD. Can hybrids be installed?

• Readout pitch is 71 mm.
• Number of channels per DSSD (512 signals in 8mm
  width) is 4-5 times denser than SVD2.
• Multi-layer kapton flex circuit solves the
  readout density issues.

10
Assembly

• All strips can be read out
• The kapton flex circuit is assembled as follows.
• Wire bonds are done at sensor edges.
• P-side and n-side are symmetric

11
Readout overview

• Experience of Belle SVD2 L1 sensor
• 10occupancy /(50mm77mm1 msec shaping)
• Super KEKB 20 times larger background
• Strip area 1/5 of Belle SVD2 (striplet)
• Additional 1/10 of shaping time gives a 1/50
  occupancy.
• Expected trigger rate 30 kHz
• With pipeline length of 3 msec readout time of
  3 msec, 30 kHz trigger rate causes relatively
  small dead time (needs evaluation). Above 30 kHz,
  dead time goes up rapidly.
• Z-trigger from VTX
• Z information is useful for reducing
  beam-background events.
• DAQ people requests the Z trigger from VTX
  becomes to be ready in 15 msec from the event
  timing.

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Readout chip APV25

• Operation at Super Belle _at_42.3 MHz clock
• 4.0 msec pipeline length
• 3.0 msec analog output scan small dead time upt
  to 30kHz trigger rate.
• Shaping time is adjustable between 50 and 100
  nsec depending on background level.

• Designed for the CMS silicon tracker
• 50 mm pitch, 128 ch/chip.
• 192 stage analog pipe line.
• Readout multiplexing all channels.
• Built-in deconvolution circuit will not be used.
• Radiation tolerance?30 Mrad
• Noise (246 36/pF) enc.

L0 trigger
Analog output
192 stage Analog Pipeline
128 channel multiplexer
Shaper
preamp
Inverter
13
Z vertex trigger from VTX

• APV25 needs a trigger (L0) from DAQ within 3
  msec from an event.
• The internal delay and analog multiplexing(MPX)
  takes 7 msec at max.
• This analog multiplexing is not pipelined.
  Therefore, the subsequent steps can not be fully
  pipelined.
• Hit cluster search and trigger decision 5 msec.
• Summing up, L1 trigger from VTX is ready at 15
  msec.
• If two triggers come to APV25 almost together,
  the second SVD trigger decision is done at least
  3 msec later than the first decision because of
  MPX.
• The second trigger is available at 20 msec.
• If trigger decision is given up for the 2nd
  event, 15 msec latency can be regained.

Event timing
L0 trigger from GDL
APV25 internal
Analog Multiplex
Track finding in VTX
L1 trigger from VTX
20
0 3 5 7 10
15
14
RD items

• Finalize the detector configuration
• Material budget in B-factory is limited.
• Minimize material in acceptance.
• Design detector support system and ladder
  structure.
• Continue pixel detector RD
• Backend electronics becoming more complex and
  important.
• 2-3 time of channels.
• 10 times of data
• Radiation hardness of sensors.
• Design a dedicated readout chip that improves
  the performance of Super Belle.

15
Summary

• Basic requirements to VTX can be fulfilled with
  striplet sensors and APV25 readout.
• In order to improve robustness of vertexing
  against the background at higher luminosities,
  preparation of pixel sensors is essential.
• In parallel, design of a dedicated front-end chip
  may be helpful to improve the performance of the
  VTX system.