Engineering Applications on

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• Engineering Applications on
• NASAs FPGA-based Hypercomputers
• By
• Olaf.O.Storaasli_at_nasa.gov
• Analytical Computational Methods Branch
• NASA Langley Research Center
• Hampton Virginia
• 7th Military Aerospace Programmable Logic Device
• (MAPLD) International Conference
• Reagan Center, Washington DC
• September 10, 2004

Field-Programmable Gate Array
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Contents
Background Hardware, Gateware Current
Algorithms Applications CPU-FPGA,
FPGA Future New Spacecraft Hypercomputer
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NASA Reconfigurable Hypercomputers
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04
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Computing Faster Without CPUs
GOAL Explore Engineering Applications on
NASAs FPGA-based Hypercomputers
TEAM Drs. Olaf Storaasli, Jarek Sobieski
Robert Singleterry,
Dave Rutishauser, Joe Rehder, Garry Qualls,
Robert Lewis
Students MIT Harvard VT Brown UVA JPMorgan Case
Pitt, Governors School
PARTNERS Starbridge Systems (FPGA H/W VIVA
S/W) NSA, USAF, MSFC, AlphaStar
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VIVA Custom Chip Design
What Graphically code FPGAs drag drop vs
text)
VIVA Menu
Traditional Code 1D do i 1, 1000
C AB end do
How Converts icons-transports to FPGA circuit
Why near-ASIC speed (w/o chip design )
Corelib Pre-built objects examples
Data Any type-size-precision (not fixed)
More System Description ports to any H/W
write once, run anywhere
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FPGA Use
Replace CPUs Exploit Parallelism Fully Max
Ops/cycle gt Fill FPGA VIVA/VHDL/Verilog
code Limit FPGA(s) gates
CPU FPGA Accelerator Exploit Local
Parallelism Max kernel Ops/cycle C/FORTRAN
calls VIVA kernel Limit FPGA gates Amdahls Law
CPU
Axb NASA GPS
50 line kernel 95 CPU Time Move to FPGA
28k lines FORTRAN
Cray XD1 Opterons Xilinx FPGAs
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GENOA-GPS Port
GENOA Analysis/Design (AlphaStar)
GPS Matrix Equation Solver (NASA) Structural,
EM, acoustic analysisdesign Most Computations
in 50-line kernel kernel coded VIVA-GPS VIVA2.4
gt large applications ongoing
(NASA-AlphaStar-Starbridge)
Progressive Failure, Reliability,
Durability Manufacturing,Virtual Test, Life
prediction Calls GPS Shuttle re-entry wing
damage analysis time 660 hours gt minutes (Goal)
Finite Element Model
99 NASA Software-of-the-Year
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Columbia Burn-thru Analysis
Leading Edge FEM
Leading Edge
Insulation Fracture 230 Sec
RCC-Tseal Fracture 503 sec
Spar Fracture 500 sec
Time
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FPGA Use
Replace CPUs Exploit Parallelism Fully Max
Ops/cycle gt Fill FPGA 100 VIVA code Limit
FPGA(s) gates
CPU FPGA Accelerator Exploit Local
Parallelism Max kernel Ops/cycle C/FORTRAN
calls VIVA kernel Limit FPGA gates Amdahls Law
Maximize Performance via Parallelism
Adds/FPGA 16 32 128 256 512 640
FPGA used 1 2 8 16 41 51
109 Ops 4 8 34 77 154 192
1000 adds/clock cycle gt 1011 Ops/sec (1
add/cycle on CPUs)
Cray XD1 Opterons Xilinx FPGAs
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Memory FPGA SDRAM- keep action on/near FPGA
-
2-8GB SDRAM (large applications)
144x 2KB blocks RAM
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File I/O

• FileIn/FileOut in Corelib
• Transfers 2 KB blocks (Disk ? FPGA RAM)
• User can access FPGA RAM 4 Bytes at a time

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Add Files in Parallel

• Read 2 files gt Store in FPGA RAM gt files gt
  Write result

R
S

W
R
S
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Parallel Adds Faster- same file size -
CPUs (1 add)
100
92
90
80
File size
70
4KB
60
Time in cycles
8KB
46
50
16KB
Log. (8KB)
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Log. (4KB)
Log. (16KB)
30
23
20
10
0
2
0
4
8
12
16
20
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Number of FPGA Adders used
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Algorithms Developed

• Matrix Algebra V, M, VTV, MxM,GCD,

• n! gt Probability Combinations/Permutations

• Cordic gt Transcendentals sin, log, exp, cosh

• ?y/?x ?f(x)dx gt Runge-Kutta CFD, Newmark
  Beta CSM

• Matrix Equation Solvers Ax b, Gauss
  Jacobi

• Analog Computing digital accuracy

• Nonlinear Analysis reduces NL time

• Structural Design Optimization

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Applications VIVA Code
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Gauss-Jordan A x B Solver
VIVA code solves n equations.
gt
Ex x0 x1 x2 0 x0 2x1 2x2 4 x0
2x1 x2 2
x0 4 x1 -2 x2 -2
Run on hypercomputer emulator, then FPGA
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Spring-Mass Solver
f
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Cellular Automata
Parallel Stephen Wolfram - A New Kind of
Science Complexity via simple interactions w/o
PDEs CFD gt Structures
Cell-neighbors interactions simple compute/cell
d
P
FEA solution
Cellular Automata solution
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Cantilever Beam Optimization
Constants L 24 W 3 P 20 lbs
0.097 lbs/in3 Constraint Stressallowed 40K
lbs/in2
Find thickness, d, to minimize
where
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VIVA FPGA Code Minimizes Beam Weight
VIVA Results d 0.156 (0.155 exact) Minimum
weight 1.09 lbs (1.082 exact)
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a bold new course into the cosmos
Reconfigurable Scalable Computing (RSC)
for Space Applications - 14.8M
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• Spirit Opportunity Rovers
• 6 Radiation-tolerant FPGAs
• 1M gates _at_ 100kRads
• -----------------------------------------
• Next
• 6M gates _at_ 200kRads

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What Reconfigurable Scalable Computing (RSC) for
Space Applications Who Langley, Goddard, NSA,
Starbridge, Jefferson Lab, ASRC, Queensland When
4 years (FY 05-08) How 14.8M Goal
Effective-affordable processing for moon Mars
missions Plan Design-implement-demonstrate RSC
for space applications Hardware Stacked scalable
FPGAs Gateware Conventional (MPI/Linux)
Special (VIVA) More
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Summary
Hardware Exploiting advanced FPGA-based systems
FPGAs Rapid growth, inherently //, flexible,
efficient
VIVA Powerful growing (tailored to NASA needs)
Applications - Many Engineering algorithms (VIVA
gt FPGAs)
- GPS-VIVA gt CPUFPGA accelerator
Speed 640 ops/cycle (2x1011 ops/sec) measured
Future Reconfigurable Scalable Computing for
Space
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The End