Aggregated Circulant Matrix Based LDPC Codes

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Aggregated Circulant Matrix Based LDPC Codes

• Yuming Zhu and Chaitali Chakrabarti
• Department of Electrical Engineering
• Arizona State University, Tempe

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Outline

• Introduction to LDPC codes
• Iterative decoding of LDPC codes
• Aggregated Circulant Matrix (ACM) based LDPC
  codes
• Construction algorithm
• BER performance
• Decoder architecture
• Concluding remarks

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Introduction to LDPC codes

• LDPC codes are linear block codes with sparse
  parity check matrix. (Low complexity)
• Can be represented by bipartite (Tanner) graph.
• LDPC codes were proposed by Gallager in 1962.
  Rediscovered in 90s because of the success of
  Turbo codes.
• Adopted in IEEE 802.16e (WiMax),10G BaseT,
  DVB-S2, IEEE 802.11n (in consideration)

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Introduction (contd.)

• LDPC code is Shannon limit approaching.
• Chung (Trans. IT, Feb 2001) reported 0.0045dB to
  AWGN channel Shannon limit with irregular LDPC
  code.
• Very simple data path.
• Potential to achieve massive parallelism and high
  throughput.
• 1G bps LDPC decoder (Blanksby and Howland 2001)

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Related Work

• High speed LDPC decoder architectures
• C. Howland 2001(Fully Parallel)
• T. Zhang 2001 (Partially Parallel)
• M.M. Mansour 2003 (Partially Parallel)
• D.E. Hocevar 2004 (Partially Parallel)
• Partially Parallel decoding for sub-matrix with
  multiple shifted identity matrices
• Z. Wang 2005 (With restriction on the shift
  values for geometrical LDPC codes)

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Outline

• Introduction to LDPC codes
• Iterative decoding of LDPC codes
• Aggregated Circulant Matrix (ACM) based LDPC
  codes
• Construction algorithm
• BER performance
• Decoder architecture
• Conclusion and future work

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Code graph and decoding

• Iterative decoding
• Belief Propagation (BP)
• Bit nodes send their belief information
  (likelihood ratio, usually in LOG domain)
• Check nodes gather the information and update the
  corresponding bit nodes.

An example of (2,3) regular LDPC
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Iterative decoding algorithm
BP
Min-Sum
?-Min
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Circulant matrix based LDPC code

• Partial parallel implementation with ordered
  sub-matrix in H matrix.
• Scheduling of the belief information update.
• Check node based
• Variable node based

Each element in the Hb matrix is a circulant
shifted version of identity matrix. (Tanner 2004)
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Layered BP algorithm

• Layered BP algorithm schedules in row order.
• The rows in one block row can be processed in
  parallel.
• Pipelining is a common technique to increase the
  throughput.
• However, the throughput increased by pipelining
  is limited if there are data dependencies.

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Outline

• Introduction to LDPC codes
• Iterative decoding of LDPC codes
• Aggregated Circulant Matrix (ACM) based LDPC
  codes
• Construction algorithm
• BER performance
• Decoder architecture
• Conclusion and future work

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Aggregated Circulant Matrix (ACM) based LDPC

• Idea Remove the data dependency between the
  block rows in the parity check matrix.
• Method Perform aggregation to reduce the
  non-zero sub-matrix within each block column.
• Outcome Throughput is doubled with a small
  increase in data-path.

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Construction algorithm for ACM

• First, construct Hb matrix with designed degree
  distribution.
• Aggregation
• It does not change the degree distribution.
• For Hb of size MxN, make sure (i,j) and (iM/2,j)
  does not contain I simultaneously.
• The decoding of block rows is scheduled as 0,
  M/2, 1, M/21, , M/2-1, M.

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Hb matrix of ACM based LDPC
Original
Aggregated
Reordered
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BER performance of ACM
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Bit Update Algorithm
m1
m
m2
Regular Sub-matrix
ACM Sub-matrix
n
n

• In parallel decoding of regular circulant matrix
  based LDPC, each bit node is updated only once.
• However, in the parallel processing of ACM LDPC,
  the bit update information could come from
  different rows that are being processed
  simultaneously.
• Some mechanism is needed to combine the multiple
  bit update information.

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Bit Update for ACM
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ACM LDPC decoder architecture
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Synthesis result

• The decoder was synthesized with TSMC 90 nm lib.
• The decoder achieved 930 Mb/s throughput when
  clocked at 300 MHz for a rate 4/5 code.
• Compared with the regular LDPC code, the
  data-path of the ACM LDPC decoder increased by
  only 20, while the throughput increased by a
  factor of 2.
• The data-path contributed 25.6 of the area of
  the overall decoder.

Arch. 16-Adder/XOR Tree Adder LUT MUX
Regular 31 1488 992 -
ACM 31 1488 992 186
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Outline

• Introduction to LDPC codes
• Iterative decoding of LDPC codes
• Aggregated Circulant Matrix (ACM) based LDPC
  codes
• Construction algorithm
• BER performance
• Decoder architecture
• Conclusion and future work

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Concluding Remarks

• The proposed ACM LDPC code has comparable
  performance with the regular LDPC codes.
• The advantage is that it can be decoded with a
  two-fold increase in the throughput at the
  expense of only 20 increase in data-path
  complexity.
• Efficient implementation of the aggregation
  algorithm with more than 2 identity matrices is
  still an open problem.

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Thank You!!

• Questions?

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Aggregation example
The example shows the case for aggregating (i,j),
(i,k), (iM/2,j), (iM/2,k). If the difference in
row index is not M/2, the shift values may vary.