Verification and Validation of Programmable Logic Devices

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Verification and Validation of Programmable Logic
Devices

• James A. Cercone Ph.D., P.E.,
• Chair and Professor of Computer Science
• WVU-Tech
• Michael A. Beims
• Senior Systems Engineer
• Science Applications International Corporation
• Kenneth G. McGill
• National Aeronautics and Space Administrations
  IVV Facility

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Abbreviations
IVV Independent Verification and
Validation VV Verification and
Validation PL Programmable
Logic FPGA Field Programmable Gate
Array VHDL VLSI (Very Large Scale Integration)
Hardware Design Language
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PLD/FPGA Software

• Designs are tested for
• Functionality
• Boundary conditions
• Operational simulation, electrical criteria
• Designs are not routinely subjected to
• Formal Verification and Validation (VV)
• Independent Verification and Validation
• Existing VV methods adaptable to designs (e.g.
  Fagan and Gibbs inspections)

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Pilot Project

• Utilize a current NASA Space System Project
• A good candidate has
• Significant reliance on PL devices for critical
  spacecraft control.
• Significant reliance on PL devices for critical
  science instrument functionality.
• An ongoing IVV process with an interface to the
  Project

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Relevance to Safety and Mission Assurance

• Design methodologies for PLD/FPGAs widely vary
• Design teams do not always follow the proven
  practices of software design
• Problems observed in design reviews at satellite
  vendors
• Late in life cycle hardware changes have been
  driven by faulty PLD logic

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Some types of defects

• May go undetected during compilation and
  simulation
• Reset related
• Reset inputs derived from sources external to
  FPGA
• Outputs and internal inputs in unknown state
  during reset
• Clocking related
• Poor clocking strategies
• Asynchronous designs crossing clocking barriers

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Types of Defects (cont.)

• Coding practices related
• Coding style mixing of structural and
  behavioral modeling
• Unstable and unnecessary code circuitry
  included in design
• Inappropriate use of commercial core codeware
• State Machine related
• Poor design of state machines (such as
  unintentional race and dynamic hazards)
• Incorporation of One Hot design Finite State
  Machine Designs that have excess unused states
• Transient related
• Susceptibility to single event effects
• Startup transients created by unused (programmed)
  input/output pin connections

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Methods and Procedures

• Collection of existing PLD/FPGA fault data from
  NASA users
• On site visits and direct contact with NASA
  PLD/FPGA designers
• Investigate VV methodologies that may be adapted
• Inspections
• Fagan and Gibbs
• Other Software Code analysis methods
• Consideration of compiler specific variations
• Attributes not apparent during simulation (e.g.
  the number of flip-flops used for finite state
  machines.)

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Technology Transfer

• Appears to be a critical need for an upcoming
  space telescope
• Large number of FPGAs for domain specific
  optimized data compression
• High complexity logic
• Numerous design iterations
• Size of the logic may need a larger die late in
  the life cycle of the instrument
• Results applicable to other developers
• A spacecraft related to this telescope
  experienced an FPGA design defect that required a
  hardware change late in the life cycle
• Results can be applied to future missions

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Success Criteria

• a) Identify PLD/FPGA design logic faults.
• b) Identify applicable existing methodologies
  by tracing design defects to their common cause.
• c) Suggest enhancements to the design phase,
  peer and design reviews.
• d) Provide field prototyped training materials
  for PL software VV.
• e) Successfully complete a pilot project.

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Uniqueness of Research

• FPGA software is not currently required to
  undergo VV evaluation according to
• Previous studies and standards such as the FAA
  DO-254
• Some European based studies
• No specific / current guideline for PLD/FPGA IVV
• Methodology has not evolved much beyond the
  classical sequential development methodology of
  specify requirements, create the design, code,
  simulate and test.

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Research Team

• James A. Cercone Ph.D., P.E.,
• Chair and Professor of Computer Science
• WVU-Tech
• Michael A. Beims
• Senior Systems Engineer
• Science Applications International Corporation
• William Clark
• Associate Professor of Computer Science
• WVU-Tech
• Sidney Valentine
• Assistant Professor of Electrical Engineering
  Technology
• WVU-Tech

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