Basic Processing Unit (Chapter 7)

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Basic Processing Unit(Chapter 7)
http//www.pds.ewi.tudelft.nl/iosup/Courses/2011_
ti1400_7.ppt
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Problem How to Implement Computers?
Computers
Data representation, conversion, and
op.Instruction repr. and use
Lectures 3,4,5,6
Programmable Devices
Memory organizationProgram sequencingvon
Neumann archi.Instruction levels
Lecture 2
Digital logicMemory elementsOther building
blocks (Multiplexer,Decoder)Finite State
Machines
Circuit Design
Lecture 1
Why Computer Organization Matters?
History of Computing(1642-2011)
Lecture 0
3
Problem
instruction
?
y
Decoder
f
ALU
a
y
Reg
4
Lecture 2Von Neumann Architecture
Memory
(Central) Processing Unit
TEMP_A TEMP_B RESULT
arithmetic unit
Input
IR
CONTROL
Output
PC
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The Processing Unit

1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms

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6
Basic Processing Cycle

• Assume an instruction occupies a 32 bit single
  word in byte addressable memory
• Basic cycle to be implemented
• 1. Fetch instruction pointed to by PC and
• put it into the Instruction Register (IR) IR
  ? M(PC)
• 2. Increment PC PC ? PC 4
• 3. Perform actions as specified in IR

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Organization
CPU bus
Decoder
PC
control
MAR
IR
memory bus
MDR
Register file
R0
Y
R1
R2
ALU
Rn-1
Z
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Register gating
CPU bus
Y_in
Const 4
Ri_in
x
Y
x
Ri
Select
x
ALU
Z_in
x
Ri_out
Z
x
Z_out
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Register gating
Edge-triggered D flip-flop
Multiplexer
R1_in
R2_in
R3_in
1
0
I
I
I
C
C
C
R1_out
R2_out
R3_out
1 bit of common bus line
Tri-state gate high impedance iff Ri_out0, Q
iff Ri_out1
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Multiple Datapaths
Bus A
R0
Y
R1
R2
R3
ALU
register file
Bus B
Bus C
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The Processing Unit

1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms

1. Register Transfer
2. Fetch from Memory
3. Store to Memory
4. Arithmetic/Logic Ops.
5. Complete Example
6. Branching Ops.

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2. Types of Operations

• Operation cycle includes
• Transfer data from register to register or to ALU
• Fetch contents of memory location and put in one
  of the CPU registers
• Store contents of CPU register in memory location
• Perform arithmetic or logic operation

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2.1. Register Transfers

• Copy contents of R1 to R3
• 1. Address_outR1
• 2. R_out
• 3. Address_inR3
• 4. R_in

R_out
CPU bus
R0
Y
R1
R2
ALU
R3
Z
register file
1. R1_out 2. R3_in
Address_out
R_in
Address_in
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2.2. Fetch from Memory (1)
Memory bus Data lines
Internal processor bus
MDR_out
MDR_outE
x
x
MDR
x
x
MDR_in
MDR_inE
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2.2. Fetch from memory (2)
e.g., Move (Ri),Rj

• 1. MAR ? Ri
• 2. Start read on memory bus
• 3. Wait for MFC response
• 4. Load MDR from memory bus
• 5. Rj ? MDR

Control Step 1
Memory Function Complete
Control Step 2
Control Step 3
Address
MAR
Data
MDR
CPU
Read
Memory
MFC
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Fetch from memory (3)
Signal Activation Sequence
Internal processor bus

• Control Step 1. Ri_out, MAR_in, Read
• Control Step 2. MDR_inE, WMFC
• Control Step 3. MDR_out, Rj_in

Ri_in
x
MDR_out
MDR_outE
Ri
x
x
Memory bus Data lines
MDR
x
Ri_out
x
x
MDR_in
MDR_inE
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Timing of the Operation
2.2. Fetch from Memory (4)

• 1. Ri_out, MAR_in, Read
• 2. MDR_inE, WMFC
• 3. MDR_out, Rj_in

1
2
3
CLK
MAR_in
address
MAR to Mem.Bus
New Address
Read
MR
Mem.Read Cmd.
MDR_inE
Data
Mem.Bus to MDR
Value
MFC
Mem.Fnc.Complete
MDR_out
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2.3. Store to Memory
e.g., Move Rj,(Ri)

• 1. Ri_out, MAR_in
• 2. Rj_out, MDR_in, Write
• 3. MDR_outE, WMFC

Address
Data
Memory
CPU
Write
MFC
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2.4. Arithmetic Operation
ADD R3,R2,R1
Step Action 1. Address_out ?
R1 Y_in R_out 2. Address_out ?
R2 R_out F_alu ? ADD Z_in ?? Address_in ?
R3 Z_out R_in
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Register Transfers
1. Address_out ? R1 Y_in R_out
R_out
CPU bus
R0
Y_in
Y
R1
R2
ALU
R3
Z
register file
Address_out
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Arithmetic Operation
ADD R3,R2,R1
Step Action 1. Address_out ?
R1 Y_in R_out 2. Address_out ?
R2 R_out F_alu ? ADD Z_in ?? Address_in ?
R3 Z_out R_in
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Register Transfers
2. Address_out ? R2 R_out F_alu ? ADD Z_in
CPU bus
R_out
R0
Y_in
Y
R1
R2
F_alu
ALU
R3
Z_in
Z
register file
Address_out
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Arithmetic Operation
ADD R3,R2,R1
Step Action 1. Address_out ?
R1 Y_in R_out 2. Address_out ?
R2 R_out F_alu ? ADD Z_in ?? Address_in ?
R3 Z_out R_in
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Register Transfers
?? Address_in ? R3 Z_out R_in
CPU bus
R0
Y
R1
R2
ALU
R3
Z
register file
R_in
Z_out
Address_in
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Steps in time
CPU bus
1
2
3
Step
Y_in
Y
Y_in
ALU
Z_in
Z_in
Z
Z_out
R_in
Z_out
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Timing
Rising edge of clock
hold time
trans- mission time
delay through ALU
turn output on
R_out
data available at next register
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The Processing Unit

1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms

1. Register Transfer
2. Fetch from Memory
3. Store to Memory
4. Arithmetic/Logic Ops.
5. Complete Example
6. Branching Ops.

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2.5. Execution of a Complete Instruction

• 1. Fetch instruction
• 2. Fetch the operand
• 3. Perform operation
• 4. Store result
• Example ADD (R3),R1
• R1 ? M(R3) R1

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Execution fetch (1)
Step 1-3 Instruction fetch and PC update
Step Action 1 PC_out, MAR_in, Read Set
carry-in ALU F_alu ADD Z_in ? Z_out,
PC_in Wait for MFC 3 MDR_out, IR_in
PC ? PC 1
IR ? M(PC )
Note for architectures having PCPC4 a
different scheme must be used
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Fetch instruction
1. PC_out, MAR_in, Read Set carry-in ALU
F_alu ADD Z_in
Q Why MAR_in?
MAR_in
MAR
PC_out
IR
PC
ADD
ALU
MDR
carry
Z_in
Z
Read
WFMC
Q Why Set carry-in ALU?
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Execution fetch (2)
Step 1-3 instruction fetch and PC update
Step Action 1 PC_out, MAR_in, Read Set
carry-in ALU F_alu ADD Z_in ? Z_out,
PC_in Wait for MFC 3 MDR_out, IR_in
PC ? PC 1
IR ? M(PC )
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Fetch instruction
?. Z_out, PC_in Wait for MFC
MAR_in
MAR
PC_in
IR
PC
ALU
MDR
MDR_in
Z
Read
Z_out
Q What is read into MDR?
WFMC
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Execution fetch (3)
Step 1-3 instruction fetch and PC update
Step Action 1 PC_out, MAR_in, Read Set
carry-in ALU F_alu ADD Z_in ? Z_out,
PC_in Wait for MFC 3 MDR_out, IR_in
PC ? PC 1
IR ? M(PC )
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Fetch instruction
3. MDR_out, IR_in
Q What is loaded into IR?
MAR
IR
PC
IR_in
ALU
MDR
Z
Read
MDR_out
WFMC
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Execute
Step Action 4 Address_outR3,
R_out MAR_in Read ? Address_outR1,
R_out Y_in, Wait for MFC 6 MDR_out,
Z_in F_alu ADD 7 Address_inR1,
R_in Z_out, End
Step 4 and 5 operand fetch
Perform addition
Store Result
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Execute
4. R3_out MAR_in Read
Q Role of Decoder?
CPU bus
Read
PC
Decoder
control
MAR
IR
memory bus
MDR
register file
R0
Y
R1
R2
ALU
R3
Z
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Execute
Step Action 4 Address_outR3,
R_out MAR_in Read ? Address_outR1,
R_out Y_in, Wait for MFC 6 MDR_out,
Z_in F_alu ADD 7 Address_inR1,
R_in Z_out, End
Step 4 and 5 operand fetch
Perform addition
Store Result
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Execute
?. R1_out Y_in, Wait for MFC
Q Where does MDR read from?
CPU bus
Decoder
WFMC
PC
control
MAR
IR
memory bus
MDR
R0
Y
R1
R2
ALU
R3
Z
register file
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Execute
Step Action 4 Address_outR3,
R_out MAR_in Read ? Address_outR1,
R_out Y_in, Wait for MFC 6 MDR_out,
Z_in F_alu ADD 7 Address_inR1,
R_in Z_out, End
Step 4 and 5 operand fetch
Perform addition
Store Result
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Execute
6. MDR_out, Z_in F_alu ADD
Q Who sets F_alu to ADD?
CPU bus
Decoder
PC
control
MAR
IR
memory bus
MDR
register file
R0
Y
R1
R2
ALU
Q Why Z_in?
R3
Z
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Execute
Step Action 4 Address_outR3,
R_out MAR_in Read ? Address_outR1,
R_out Y_in, Wait for MFC 6 MDR_out,
Z_in F_alu ADD 7 Address_inR1,
R_in Z_out, End
Step 4 and 5 operand fetch
Perform addition
Store Result
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Execute
7. R1_in Z_out, End
Q Role of End?
CPU bus
Decoder
PC
control
MAR
IR
memory bus
MDR
register file
R0
Y
R1
R2
ALU
R3
Z
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The Processing Unit

1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms

1. Register Transfer
2. Fetch from Memory
3. Store to Memory
4. Arithmetic/Logic Ops.
5. Complete Example
6. Branching Ops.

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2.6. Branching
Jump PCOffset
Step Action 1-3 ltinstruction fetch as in
previous examplegt ? PC_out, Y_in 5 Offset-fiel
d-IR_out F_alu ADD Z_in 6 PC_in Z_out,
End
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Branching
?. PC_out, Y_in
CPU bus
Decoder
PC
control
MAR
IR
memory bus
MDR
register file
R0
Y
R1
R2
ALU
R3
Z
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Branching
Step Action 1-3 ltinstruction fetch as in
previous examplegt ? PC_out, Y_in 5 Offset-fiel
d-IR_out F_alu ADD Z_in 6 PC_in Z_out,
End
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Branching
5. Offset-field-IR_out F_alu ADD Z_in
CPU bus
Decoder
PC
control
MAR
IR
memory bus
MDR
register file
R0
Y
R1
R2
ALU
R3
Z
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Branching
Step Action 1-3 ltinstruction fetch as in
previous examplegt ? PC_out, Y_in 5 Offset-fiel
d-IR_out F_alu ADD Z_in 6 PC_in Z_out,
End
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Branching
6. PC_in Z_out, End
CPU bus
Decoder
PC
control
MAR
IR
memory bus
MDR
R0
Y
R1
R2
ALU
R3
Z
register file
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Conditional branching
JN PCOffset
Step Action 1-3 ltinstruction fetch as in
previous examplegt ? PC_out, Y_in If N0 then
End 5 Offset-field-IR_out F_alu
ADD Z_in 6 PC_in Z_out, End
If not Negative
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The Processing Unit

1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms

1. Hardwired
2. Micro-Programmed

Q Who sets F_alu to ADD?
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3. Control Mechanisms

• There are two basic control organizations
• Hardwired control
• Micro-programmed control

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The Processing Unit

1. Basic Processing Cycle
2. Types of Operations
3. Control Mechanisms

1. Hardwired
2. Micro-Programmed

Q Who sets F_alu to ADD?
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3.1. Hardwired ControlControl Unit Organization
CLK
Control step counter
Clock
Encoder/ Decoder
IR
Status Flags
Condition Codes
Control signals
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3.1. Hardwired ControlSeparating
decoding/encoding
Control step counter
Clock
Reset
Q Role of Run?
Step decoder
Only one set to 1
T_1
T_n
Ins_1
Status Flags
Encoder
Instruction decoder
IR
Condition Codes
Ins_n
End
Run
Z_in
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3.1. Hardwired ControlGeneration of control
signals
ADD
BRanch
T_6
T_5
T_1
Z_in T_1 T_6 . ADD T_5 . BR
time slot
Z_in
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3.1. Hardwired ControlEnd signal
Other example
End T_7 . ADD T_6 . BR (T_6 . N T_4 . /N)
.BRN
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PLAs
PLA
AND array
OR array
IR
counter
Flags
Control signals
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3.1. Hardwired ControlPerformance

• Performance is dependent on
• Power of instructions
• Cycle time
• Number of cycles per instruction
• Performance improvement by
• Multiple datapaths
• Instruction prefetching and pipelining
• Caches

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Complete CPU
Floating-point unit
Integer unit
Integer unit
Floating-point unit
Instruction unit
Integer unit
Floating-point unit
Data Cache
Instruction Cache
Bus Interface
Processor/CPU
System Bus
Main Memory
Input/ Output
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3.2. Micro-programmed control

• All control bits are organized as memory
• Each memory location represents a control
  setting/word
• The word represents the state (0/1) of each
  control signal
• Memory words are called micro-instructions
• Micro-routines are sequences of
  micro-instructions
• Control store for all micro-routines
• Micro-program counter (uPC) to read control words
  sequentially

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3.2. Micro-Programmed Control Examples of
Micro-Instructions
micro- PC_in MAR_in Addr_in Z_in ... instruction
1 0 1 00 1 ... 2 1 0 00 0 ... 3 0
0 01 0 ... .. ..
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3.2. Micro-Programmed Control Example of a
Micro-routine
Address Micro-instruction 0 PC_out, MAR_in,
Read, Set carry-in ALU, F_alu ADD,
Z_in 1 Z_out, PC_in, Wait for MFC 2 MDR_out,
IR_in 3 Branch to starting address routine
(here, 25) .......................................
..................................................
............... 25 PC_out, Y_in, if N0 then goto
address 0 26 Offset-field-of-IR_out, F_alu
ADD, Z_in 27 Z_out, PC_in, End
Fetch Instruction
Test N bit
New PC address
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3.2. Micro-Programmed Control Basic organization
Q Can this organization perform conditional
branching operations?
IR
Starting address generator
Clock
micro-PC
Control Signals
Control Store
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3.2. Micro-Programmed Control Detailed
organization
IR
Status flags
Starting/Branching address generator
Control codes
Clock
micro-PC
Control Signals
Control Store
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3.2. Micro-Programmed Control micro-PC Operation

• Micro-PC is incremented by 1, except
• After loading IR
• Micro-PC is set to first micro-instruction for
  executing machine instruction
• At End
• Micro-PC is set to first micro-instruction of
  instruction fetch routine (typically 0)
• At Branch instruction
• Micro-PC is set to the branch address

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3.2. Micro-Programmed Control Why
micro-programming?

• Flexibility
• emulation of different instruction sets on same
  hardware
• Support for powerful instructions

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3.2. Micro-Programmed Control Structure
micro-instructions

• Most simple organization 1 bit per control
  signal
• However,
• Many bits needed (e.g., 80-120 bits)
• For many signals, only one is needed per cycle
  hence they can be grouped
• Coding is possible e.g., an address instead of a
  single control bit per register

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3.2. Micro-Programmed Control Example
F1
F2
F3
F4
F5
F6
F7
F8
Field 1(4 bits) Register address_in Field 2(4
bits) Register address_out Field 3(4
bits) Other registers_in Field 4(4
bits) Function ALU Field 5(2 bit) Read/Write/No
p Field 6(1 bit) Carry-in ALU Field 7(1 bit)
WMFC Field 8(1 bit) End ............ .......
.......
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3.2. Micro-Programmed Control Forms of
organization

• Little coding horizontal organization
• Large words
• Little decoding logic
• Fast
• Much coding vertical organization
• Small control store
• Much decoding logic
• Slower
• Mixed organization

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3.2. Micro-Programmed Control Horizontal/Vertical
F0
F1
F2
F3
Horizontal
F0
F1
Decoder
Vertical
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3.2. Micro-Programmed Control Sequencing

• Thus far only branch after fetch
• No sharing of micro-code between micro-routines
• Micro-subroutines lead to more efficient control
  store

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3.2. Micro-Programmed Control Multi-way branching

• Number of two-way branches
• disadvantage slows down
• More than one branch address in micro-instruction
• disadvantage more bits required
• bit-ORing if specified branch address

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3.2. Micro-Programmed Control Example
branch address
x x x 0 0
micro-instruction
OR
y z
part of IR
x x x y z
actual branch address
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3.2. Micro-Programmed Control Example
microroutine (1)
ADD (Rsrc), Rdst
Mode
OP code
010
Rsrc
Rdst
IR
0
3
4
7
8
10
11
bit 8 direct/indirect bit 9,10 indexed
(11) autodecrement(10) autoincrement(01)
register(00)
Instruction Format
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3.2. Micro-Programmed Control Example
microroutine (2)
Address Micro-instruction 0 PC_out, MAR_in,
Read, Set carry-in ALU, F_alu ADD,
Z_in ? Z_out, PC_in, Wait for MFC 2 MDR_out,
IR_in 3 µBranchµPC?101 (from PLA)
µPC_5,4?IR_10,9 µPC_3?not.IR_10.not.IR_9.
IR_8 ..........................................
..................................................
............... 121 Rsrc_out, MAR_in, Set
carry-in ALU,Read, F_alu ADD, Z_in 122 Z_out,
Rscr_in 123 µBranchµPC??170 µPC_0?not.IR_8,
WMFC 170 MDR_out, MAR_in, Read,
WMFC 171 MDR_out, Y_in 172 Rdst_out, F_alu
ADD, Z_in 173 Z_out, Rdst_in, End
use bits from IR for addressing mode
FETCH
autoincrement
direct
indirect
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3.2. Micro-Programmed Control Micro branch
address
Mode
OP code
010
Rsrc
Rdst
IR
9
0
3
4
7
8
10
11
/IR10./IR9.IR8
101
0 0 1 0 1 0 0 0 1
PLA
121
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3.2. Micro-Programmed Control Micro branch
address
Mode
OP code
010
Rsrc
Rdst
IR
0
3
4
7
8
10
11
/IR8
170
0 0 1 1 1 1 0 0 1
PLA
171
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3.2. Micro-Programmed Control Next-address field
(1)

• Micro-instruction contains address next
  micro-instruction
• Larger store needed
• Branch micro-instructions no longer needed

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Next-address field (2)
IR
Status flags
Condition codes
Decoding circuits
micro-AR
Control store
Next address
micro-IR
Microinstruction decoder
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3.2. Micro-Programmed Control Example
F1
F2
F3
F4
F5
F6
F7
F8
F0
Field 0(8 bits) Next address Field 1(4
bits) Register address_in Field 2(4
bits) Register address_out Field 3(4
bits) Other registers_in Field 4(4
bits) Function ALU Field 5(2 bit) Read/Write/No
p Field 6(1 bit) Carry-in ALU Field 7(1 bit)
WMFC Field 8(1 bit) End ............ PLA/ORi
ng etc
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3.2. Micro-Programmed Control Emulation

• A micro-program determines the machine
  instructions of a computer
• Suppose we have two computers M1 and M2 with
  different instruction sets
• By adapting the micro-program of M1, we can
  emulate M2

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3.2. Micro-Programmed Control Organization

• Micro-program is often placed in ROM on CPU chip
• Some machines had writable control store, i.e.
  user could change instruction set