FUTURE NANOELECTRONIC DEVICES AND THEIR APPLICATIONS

1
FUTURE NANOELECTRONIC DEVICES AND THEIR
APPLICATIONS

• Larry Cooper
• Arizona State University
• Future Directions in CAS A Day of Brainstorming
• May 27, 2005, Kobe, Japan

2
NANOELECTRONIC DEVICES AND THEIR APPLICATIONS
BASIC CONCEPT LOW POWER (1000X) HIGH SPEED
(100X) ARCHITECTURE NEW FUNCTIONALITIES
BEYOND SILICON
3
BEYOND SILICON
COMPOUND SEMICONDUCTORS FERROMAGNETIC METALS AND
SEMICONDUCTORS _________________ DEVICES ARE IN
THE EXPLORATORY PHASE A MEASUREABLE PROPERTY IS
OBSERVED WHICH CAN BE CONTROLLED WITH CURRENTS,
VOLTAGES OR MAGNETIC FIELD HOW DOES DIMENSIONAL
SCALING AFFECT OUTPUT? DOES SCALING IMPROVE
OPERATING TEMPERATURE? HOW LARGE ARE THE
CURRENTS, VOLTAGES, ETC. AND IS DISSIPATION AND
HEATING CRITICAL? WHAT ARE THE BEST
MATERIALS? WHAT ARE THE BEST CIRCUIT
ARCHITECTURES? CAN THEY BE MANUFACTURED COST
EFFECTIVELY? IS IT WORTH THE EFFORT???
4
FUTURE APPLICATIONS (MY VISION)
INTELLIGENT SENSORS NONVOLATILE-REPROGRAMMABLE
COMPUTER gtREPLACE FPGA and ASIC gtINSTANT ON
COMPUTER MOBILE COMPUTING AND COMMUNICATIONS BIO-M
EDICAL IMPLANTS gtMONITORING OF PATIENT
FUNCTIONS gtNEURAL PROSTHESES gtARTIFICIAL
RETINA AUTONOMOUS SMALL ROBOTS HIGH SPEED
DIGITAL SIGNAL PROCESSING (FASTER
COOLER) SUPERCOMPUTING MULTIFUNCTIONAL SYSTEMS
5
NANOELECTRONIC AND NANOMAGNETIC DEVICES
RESONANT TUNNELING DIODES (RTD) NANOWIRE
TRANSISTORS (NW) MAGNETOELECTRONIC
DEVICES NANOMAGNETIC DEVICES SPINTRONIC
DEVICES SINGLE ELECTRON TRANSISTORS (SET) QUANTUM
DOTS (QD) CARBON NANOTUBE TRANSISTOR
(CNT) MOLECULAR SWITCHES AND TRANSISTORS QUANTUM
COHERENCE DEVICES
6
PROPERTIES OF INTEREST
ULTRA LOW POWER DISSIPATION BATTERY LIFE HIGH
DENSITY CIRCUITS COOLER CIRCUITS HIGH
SPEED DEVICE SWITCHING CIRCUIT
ARCHITECTURES-PARALLEL COMPUTING CIRCUIT
COMPACTNESS 3 DIMENSIONAL INTEGRATION MULTIFUNCT
IONALITY NONVOLATILITY
7
SEMICONDUCTOR NANOWIRES
WHY? LOW CURRENTS ALL SEMICONDUCTORS AND MANY
OTHER MATERIALS DIFFERENT HETEROJUNCTION
DEVICES GROW ON ANY SUBSTRATE PERFECT
INTERFACES (LESS SCATTERING AND OTHER LOSS) SIZE
CONTROL (gt 10 NANOMETERS) ISSUES? DEVELOP NEW
TECHNOLOGY CIRCUIT DESIGNS AND NEW
ARCHITECTURES MATERIALS FLUCTUATION
(IMPURITIES)
8
(No Transcript)
9
(No Transcript)
10
RESONANT TUNNELING DIODE
11
WHY RESONANT TUNNELING DIODES?
INTRINSIC SWITCHING SPEED IS OVER 3
TERAHERTZ NONLINEAR I-V CHARACTERISTIC FEWER
DEVICES IN CIRCUIT IMPLEMENTATIONS (THAN
CMOS) LOW POWER DISSIPATION VERSATILE
FUNCTIONALITY-PERFORMS ALL DSP FUNCTIONS PROVEN
WAFER SCALE FABRICATION TEMPERATURE
INSENSITIVE HIGH SPEED DSP CIRCUITS-50
GHZ HYBRID DEVICE-RTD / HEMT (InGaAs/InP) 50
FEMTOSECOND PHASE NOISE CLOCKS POSSIBILITY OF
THREE TERMINAL DEVICE PHOTOSENSITIVE RESPONSE
12
100 Nanometer Diameter
13
(No Transcript)
14
(No Transcript)
15
(No Transcript)
16
(No Transcript)
17
3 TERMINAL RTD
18
(No Transcript)
19
PERMEABLE BASE-RTD
20
SINGLE ELECTRON TRANSISTORS
WHY? VERY LOW POWER HIGH DENSITY
CIRCUITS MEMORY CIRCUITS DEMONSTRATED ISSUES O
PERATING TEMPERATURE CONTROL OF DIMENSIONS AND
MATERIALS ELIMINATION OF SPURIOUS CHARGES
21
(No Transcript)
22
PROBLEMS
COMPLEXITY OF INTERCONNECTS CLOCKING OF SIGNALS
ACROSS THE CIRCUITS DEVICE TO DEVICE
VARIATIONS TEMPERATURE OF OPERATION
23
CNN-UNIVERSAL MACHINE IMAGE PROCESSING
COMPUTER
PROGRAMMABLE IMAGE PROCESSING COMPUTER ON A
CHIP 2 D ARRAY OF PROCESSING ELEMENTS HIGH LEVEL
PROGRAMMING LANGUAGE ON-CHIP A/D AND D/A IMAGE
FUSION CURRENT PROJECTS MULTI-LEVEL
CNNs INTEGRATION OF FOCAL PLANE ARRAYS ON CNN
CHIP EXPLORING NEW APPLICATIONS
ALGORITHMS TACTILE SENSING FACIAL
RECOGNITION AUTONOMOUS ROBOTS REAL-TIME IMAGE
PROCESSING FOR MEDICAL IMAGING, COLLISION
AVOIDANCE, OTHERS
24
(No Transcript)
25
Template configurations I Spatial feedback
X2 (self)
xij - state/ yij - output
x2
x2
z- bias (space invariant)
x2
zij - bias
uij - input
26
Comparison of different CNN-UM solutions
27
(No Transcript)
28
RTD BASED CNN
UTILIZE THE NONLINEAR CHARACTERISTIC OF RTD USE
RTD AS SOURCE CONTACT OF HEMT CIRCUIT MODELING
USING Q-SPICE
29
(No Transcript)
30
(No Transcript)
31
NANOMAGNETICS
LOW POWER-NONVOLATILE ELECTRONICS INTEGRATION OF
HIGH DENSITY MEMORY WITH CPU REPROGRAMMABLE
LOGIC MAGNETIC LOGIC ELEMENTS SINGLE DOMAINS IN
MAGNETIC NANOWIRES HIGH DENSITY MEMORY
32
Hybrid Hall Effect Device

• AFM of f 500 nm prototype

Ferromagnetic element (nonvolatile states)
V
Physical principle
I-
bistable ferro-magnetic film
Write pulsed I in write wire Read fringe-field
Hall effect
V negative
I
V-
Integrated operation
nonconductive region radiation damage by FIB
Materials III-Vs (e.g. InAs, GaAs) and
SOI Output 30 mV (typ.)
Write wire
B
A
C
Mark Johnson, NRL
33
(No Transcript)
34
Bilayer F film 2 bits / cell, NDRO

• 2 F elements stacked
• Each with a different moment, switching field

60 nm FeCo
75 nm Py
90 nm SiO2
35
Write 2 unique values of switching field Read
4 discrete output values
36
Nonvolatile Gates New paradigms for
Reprogrammable Logic

• Begin with existing, inflexible Field
  Programmable Gate Array (FPGA) architecture
• Use Nonvolatile HHE devices for Look Up Tables
  (LUT) in each cell and for switches that
  interconnect cells
• Result is highly flexible Reprogrammable Gate
  Arrays
• Dynamically Reprogrammable Boolean Gates
• Use 3 input terminals - A, B and Control (C) -
  and 2 clock cycles
• Control pulse dynamically determines one of the
  four basic Boolean operations AND, OR, NAND or
  NOR
• Result is latched for next, asynchronous logic
  step
• Control pulse is part of data stream Permits
  remote programming
• HHE Nonvolatile gates are also memory cells
• Integration of logic and memory is automatically
  achieved
• Chip sectors can be continuously apportioned to
  memory or logic
• Chip can be continuously (and remotely)
  reprogrammed for new functions

37
MRAM
gtBASED ON GIANT MAGNETORESISTANCE EFFECT IN
MULTILAYER METAL FILMS gtUSE OF TUNNELING
MAGNETORESISTANCE FOR LARGER EFFECTS gtINTEGRATED
NON-VOLATILE SRAM gtSTAND ALONE HIGH DENSITY MEMORY
38
FET is used for read-addressing.
One FET per bit is required.
39
Vertical GMR Memory Design

A memory cell
hard magnetic layers
soft magnetic layers
bit line
Nanomagnetic memory Performance improves as
magnetic element shrinks in size
40
Vertical GMR Memory (VMRAM)
Jimmy Zhu, Carnegie Mellon University
A memory cell
bit line
paired word lines
bit line
Ring shaped vertical GMR memory stack
Magnetic Switching Speed
paired word lines
read 2x0.4ns
write 0.8ns
41
D1/(4l2)
Ultimate Density
dc 10 nm
M
Energy Density ( erg/cm3)
Inner Diameter d (nm)
NiFeCo 15Å
Ultimate density 400 Gbits/in2 or 63 Gbits/cm2
42
SPIN MOMENTUM TRANSFER
N normal metal layer F1 fixed ferromagnetic
layer spin polarizer F2 free ferromagnetic
layer excitable nanomagnet
Nanopillar device Katine et al. (Cornell)
Nanocontact device Rippard et al. (NIST)
43
Advantages of Spin-Current-Switched MRAM Over
Field-Switched MRAM

• Spin transfer gives stronger torques per unit
  current than for magnetic fields,
• in devices smaller than about 250 nm.
• Improved write margin short-range forces.
• Improved density and reduced process adder (1-2
  masks instead of 3-5).
• Excellent scaling to small sizes -- switching
  currents can be minimized while
• maintaining magnetic anisotropy barriers for
  thermal stability
• Requirements for an effective spin switched MRAM
  Bit
• 1 Optimizing to allow smaller currents (0.1-0.2
  mA) for switching of stable nanomagnets
• 2. Higher impedances (1-10 k?) to be compatible
  with readout by silicon electronics.
• 3 Manufacturable process margins.

Dense, fast, non-volatile memory low power and
high performance embedded
44
(No Transcript)
45
(No Transcript)
46
(No Transcript)
47
(No Transcript)
48
Alternative Spin Transfer Device Reversible
Domain Wall Displacement
SEM and MFM (b) of domain wall device. Domain
wall is trapped in the left constriction
Tsoi et al. APL 83 2617 (2003)
Low Ic
Speed? Scalability? Thermal stability for high
density memory?
Grollier et al. APL 83 509 (2003)
49
Quantum-Dot Cellular Automata
A Quantum-Dot Cell

• Represent binary information by charge
  configuration

A cell with 4 dots
An Array of Cells
Neighboring cells tend to align due to
direct Coulombic coupling
50
Magnetic QCA
Magnetic nanopillar as bistable switch
Due to shape anisotropy there is a typically few
hundred room-temperature kT energy barrier
between the two stationary states.
Assigning logic values
0
1
QCA idea ground state depends on the state of
the neighbors
Ground state
Metastable state
University of Notre Dame
Center for Nano Science and Technology
51
The Nanomagnet Wire and Inverter
Magnetic Force Microscopy Image
Micromagnetic Simulation of a six-dot chain
Physical basis Antiferromagnetic coupling
between singledomain dots
Logic equivalent
52
Adiabatic Switching of the Nanowire
Clocked Operation
Input dot retains its magnetization
53


Integrated Nanomagnet Logic
Input realization
Output realization
Input block
Output block
CMOS postprocessor circuits
CMOS preprocessor circuits
Concept of edge-driven computing
Only dots on the edge of the structure are
accessed individually
54


Magnetic QCA - a system built on majority logic
Input 1 Input 2 Input 3 Output
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
Input 2 OR Input 3
Input 2 AND Input 3
55
POSSIBLE NANODEVICE ARCHITECTURES
EDGE DRIVEN COMPUTERS PIP-PROPAGATED INSTRUCTION
PROCESSOR QCA-QUANTUM CELLULAR
AUTOMATA MQCA-MAGNETIC QUANTUM CELLULAR
AUTOMATA CNN-CELLULAR NONLINEAR NETWORK FIELD
REPROGRAMMABLE GATE ARRAY MULTIVALUE
LOGIC/MULTIVALUE MEMORY 3 DIMENSIONAL
MULTIFUNCTIONAL PROCESSORS PARALLEL COMPUTING
56
END
57
Semiconductor Spintronics
Resonant Interband Tunneling Diode
Ferromagnetic Semiconductor p - GaMnSb
AlSb
AlSb
Electrons tunnel through SPIN-POLARIZED valence
band states of quantum well
GaMnSb
E
c
InAs
InAs
E
v

• bias dependent spin-polarized source
• gated RITD (with polarized emitter)

Jonker
58
RTD / GMR Hybrid Devices
exchange coupled
dR/R 28
T 300 K
May 2000
59
RTD - GMR Hybrid
MOnostable-BIstable Logic Element MOBILE
Maezawa Mizutani (1993)
MOBILE INVERTER
Bias
Input
Output
High (1)
Low (0)
0 V
Jonker
60
(No Transcript)
61
(No Transcript)
62
Device opportunity spintronic currents without
injection
Bias
M
Read
Write
Fabricated prototype device structure
integrating electronics, magnetics, and
photonics
63
(No Transcript)
64
SPINTRONICS
ELECTRON SPIN CONTROLLED ELECTRONICS ULTRA-LOW
POWER MULTIFUNCTIONAL DEVICES HIGH
SPEED ISSUES MATERIALS (LOW OPERATING
TEMPERATURE) MOBILITY NEED ELECTRON
INJECTION (May be useful for optical
applications, I.e. THz switching and
modulation) (Electron spin control for quantum
information processing)
65
MATERIALS-BEYOND SILICON CMOS
III-V COMPOUND SEMICONDUCTORS HETEROJUNCITONS NA
NOWIRES FERROMAGNETIC METALS MAGNETOELECTRONICS
MAGNETIC NANOWIRES-SINGLE DOMAINS MAGNETIC
SEMICONDUCTORS SPINTRONICS SILICON/GERMANIUM CAR
BON NANOTUBES MOLECULAR SWITCHES
66
(No Transcript)
67
Reprogrammable Logic FRePGA

• Need nonvolatile switch, ME FET
• Then FRePGA chip uses ME for LUT and
  interconnect switches
• Programming of FRePGA is by software - NO ROM
  needed
• ME is nonvolatile values for LUT and
  interconnect switches are always there Instant
  ON
• Flexibility Reprogrammable
• Hardware upgrade is by software
• Reprogram blocks at any time by storing new
  values in ME LUT
• Blocks can also be apportioned for use as
  nonvolatile RAM, as needed
• ME cell size lt SRAM so Block Density increases by
  2x

ME LUT
Xylink, Infineon