Data Synchronization Issues in GALS SoCs

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Data Synchronization Issues in GALS SoCs
ICS- FORTH

• Rostislav (Reuven) Dobkin and Ran
  GinosarTechnion
• Christos P. SotiriouFORTH

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Outline

• The Problem
• Synchronization Failures in GALS SoCs
• Three solutions
• Timing verification
• Synchronizers
• Locally-delayed clocks
• Analysis

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GALS with Stoppable Clocks

• A GALS Module contains
• Synchronous Island
• Local clock generator
• Self-timed wrapper (can stop the local clock)
• Handshake for inter-modular communications,

Moore et al., Point to point GALS interconnect,
ASYNC 2002 Villiger et al., Self- timed Ring for
Globally- Asynchronous Locally- Synchronous
Systems, ASYNC 2003
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Data Synchronization
Moore et al., Point to point GALS interconnect,
ASYNC 2002 Villiger et al., Self- timed Ring for
Globally- Asynchronous Locally- Synchronous
Systems, ASYNC 2003
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Synchronization Failure
Due to clock tree delay, the previous clock rise
may conflict with the handshake
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Synchronization Failure RACE !
Conflict Condition DCLK d x
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Conflict / Safe Zones
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Three Solutions
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Solution 1Timing Verification
SAFE
SAFE

SAFE

• Extract delays
• Verify that DCLK falls inside the SAFE zones

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Solution 1Matched Delay Port Control
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Solution 1 Disadvantages

• Clock tree delays must be re-verified after each
  layout iteration
• The solution is sensitive to thermal and voltage
  variations

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Solution 2Two-Flop Synchronizer

• Low bandwidth
• Resolution time one clock cycle
• Data Cycle At least 3 clock cycles

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Solution 3Locally Delayed Latching
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Solution 3Time Budget
Clock Y
MS
DCTRL
Y1
Conflict
Port Wins
MS
DCTRL
Y1
Clock Wins
Asynchronous Controller Delay
MUTEX Metastability Resolution
Clock Y1High-Phase
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How much resolution time?
REQUIRED MTBF (YEARS)

• Less than 50 FO4 delays needed to resolve
  metastability
• ASIC / SoC clocks are slow T gt 100 FO4 delays
• Conclusions
• Fast clocks Half a cycle is budgeted for M/S
  resolution
• Slower clocks (Tgt200 FO4) Quarter cycle

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Solution 3Operating Modes
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Solution 3A. Decoupled Input Port
DCTRL DR3?DO? DI?L-?R2-
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Solution 3B. Decoupled Output Port
DCTRL DA4 ?A1 ?A3-
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Solution 3C. A Simpler Input Port
DCTRL DLATCH DTX ACK ? REQ-
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Solution 3Analysis
Clock Y
MS
DCTRL
Y1
Conflict
Minimal Clock High-Phase, THP 3 FO4 gate delays
T/4 for M/S Resolution
Asynchronous Controller Delay

• Example T160 FO4 gate delays. ?Constraint

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Solution 3Simulations
Circuit Critical Path Latency (0.35m) InverterFO4 delays
Decoupled Input Port R3?Do?Di?L?R2 3.13 ns 24
Decoupled Output Port A4?A1?A3 1.81 ns 14
Simple Input Port with Decoupled Output Port Latch Delay?A2?R2 2.13 ns 16
These results are based on data bus width of 16
bits
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Summary

• Design of arbitrated clocks for GALS SoCs must
  consider clock tree delays to control the risk of
  synchronization failures
• Presented three solutions
• Extract the delays and verify timing
• Employ 2-flop synchronizers or matched-delay
  async ports (low bandwidth)
• Employ locally-delayed ports(high bandwidth)

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Synchronization Failures (3)

• Starting from X, the conflict occurs when
• (6)?(23)?(15)?(16) (5)

(I)
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MUTEX MTBF
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A. DIP STG
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B. DOP STG
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Locally Delayed Latching Full Custom Circuit
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Locally Delayed Latching Full Custom Wave
Diagram
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LDL Constraints