Network On Chip: A New SoC Paradigm

1
Network On Chip A New SoC Paradigm

• Seminar Presentation
• Shantanu Gupta
• 01010123
• Under Guidance of
• Dr. Santanu Chattopadhyay

2
Outline

• Motivation - Shared Medium Networks in SoC
  communication
• Network On Chip (NoC) an obvious alternative
• OSI Layered Model in NoC
• Few NoC Results
• Challenges and Research Avenues in NoC
• Summary

3
Growing Chip Density
1998 Asic - 0.35 mm
2003 SoC - 0.1 mm
Memory, I/O
P

• Hundreds of Processing Elements (PEs) on a single
  chip
• Design Complexity
• Efficient high performance interconnect
• Scalability of communication architecture

4
Design Productivity Gap
Moores Law The capacity of integrated chips
doubles every 18-20 months.
108
106
1
Time
65 75 80 85
90 95 2000
5
SoC Communication Basics

• Shared Medium Common Buses, Data Paths.
• Hybrid Networks Hierarchical buses, Multiple
  Backplane. Local communication on shared bus,
  packet switched network on higher levels.
• Direct and Indirect Network Presence of Network
  Interface Block, supports P2P communication.

6
Outline

• Motivation - Shared Medium Networks in SoC
  communication
• Network On Chip (NoC) an obvious alternative
• OSI Layered Model in NoC
• Few NoC Results
• Challenges and Research Avenues in NoC
• Summary

7
Shared Medium On Chip Buses

• On-chip Bus design
• Bus topology, mapping
• Bus data transmission
• Bus segment widths, DMA size, data packet size
• Bus control
• Priorities
• Basic operation
• Arbitration of accesses to the shared bus
• Data transfer

8
Advantages

• Easy Design
• Low Cost
• Good utilization

Pentium Architecture
9
Disadvantages

• Energy Inefficiency
• Non scalable Bandwidth
• Physical limitation on Frequency
• Central arbitration is a bottleneck
• Long wire delays Clock skews
• Long wire capacitative disadvantages

SoC Nightmare
10
Solutions and Alternatives

• Regular architecture Instead of irregular
  global wiring
• Point to Point Communication Enables multiple
  connection, distribution of load
• Packet Based Communication
• GALS Globally Asynchronous and Locally
  Synchronous

11
Outline

• Motivation - Shared Medium Networks in SoC
  communication
• Network On Chip (NoC) an obvious alternative
• OSI Layered Model in NoC
• Few NoC Results
• Challenges and Research Avenues in NoC
• Summary

12
NoC Network of Computational and Storage
resources

• Generic platform for System Design
• Computational resources Processor cores, FPGAs
• Reuses third party components
• Storage Distributed
• Interconnect
• All resources have an address
• Resources interconnected by network of switches
• Communication by packet transmission
• Configurability
• Hardware and Software programmability

Network Logic
Computational Resource
13
NoC verses Large Computer Networks

• Routers on Planar Grid Topology
• Short reliable PTP links between routers
• Light weight protocols, no legacy protocols to be
  compliant with
• Hardware implementation of protocols ? No
  Software
• No dynamic changes and failures
• Custom Network Design You design what you need
• Unique VLSI Constraints
• Area-Routers and links
• Power

14
Why NoC?

• Inherent Non-determinism due to increasing system
  complexity
• Energy and device reliability
• Requirement of modular approach, structured
  layout
• Re-usability, and re-programmability
• It provides solution to most of the SoC problems

15
Advantages of NoC

• Efficiency
• Speed, Higher Bandwidth
• Area
• Power Consumption
• Scalability
• Concurrency, effective spatial reuse of resources
• Modularity Design Productivity Improvement
• Higher levels of abstraction By OSI Layered
  model

16
Outline

• Motivation - Shared Medium Networks in SoC
  communication
• Network On Chip (NoC) an obvious alternative
• OSI Layered Model in NoC
• Few NoC Results
• Challenges and Research Avenues in NoC
• Summary

17
OSI Layered Model

• Open System Interconnect (OSI) Model is general
  purpose network model
• NoC employs at present Physical layer, Data Link
  Layer and Network Layer in detail

18
Physical Layer or Network Topology

• Considered unreliable due to physical and power
  constraints
• High speed communication is a necessity
• Deep submicron effects, noise, signal integrity
• Power consumption
• Clock distribution - GALS
• Memory Integration (50-80 of chip)

19
Physical Layer Continued

• Physical layer topology for NoC can be subdivided
  as
• Indirect Network (with switches)
• Indirect Mesh - Popular
• Eclipse
• SPIN Fat Tree
• Direct Network (no intermediate switch)
• Octagon - Popular
• Direct Mesh
• Torus

20
Topologies some examples
1D Mesh
Ring
2D Mesh
Torus
Fat tree
Butterfly
21
Indirect Networks examples
Spin Network
Mesh Network
22
Direct Network examples
PE Tile
Octagon
Mesh
23
Data Link Layer

• Requirement - To increase the reliability of the
  physical link up to a minimum required level
• Packetizing data
• Performance vs. error probability tradeoff
  depending on packet size
• Buffering
• Error control
• Flow control
• alternating-bit, go-back-N and selective repeat
• Contention based approaches cause noise

Application
Transport
Network
Data link
Physical
24
Network Layer

• Requirement To implement end-to-end delivery
  control in network architectures with many
  communication channels
• Switching algorithms
• Circuit, packet and cut-through switching
• Routing algorithms
• Deterministic routing good for regular traffic
  pattern
• Adaptive routing good for irregular traffic
  (case of SoCs)

Application
Transport
Network
Data link
Physical
25
Packet Switching - Popular

• Packet can take any path to the destination
• Connection-less
• Non-deterministic delay due to buffer and
  congestion
• No QOS guarantee
• Flow and congestion control needed compared to
  circuit switch network

26
Packet Routing Schemes
27
Packet Routing Schemes cont.
28
Transport Layer

• Requirement To provide reliable end-to-end
  services (e.g. TCP). Still not a full fledged
  part of NoC design
• Packetization at the source
• Re-sequencing and reassembling at the
  destination
• Flow control and negotiation
• Deterministic approach service quality
  guarantee with resource underutilization
• Statistical approach more efficient but no
  quality guarantee

Application
Transport
Network
Data link
Physical
29
Outline

• Motivation - Shared Medium Networks in SoC
  communication
• Network On Chip (NoC) an obvious alternative
• OSI Layered Model in NoC
• Few NoC Results
• Challenges and Research Avenues in NoC
• Summary

30
Effect of Buffer Size and Network Traffic on Drop
Probability on a 5x5 Mesh

• Channel Effective Width 256 bits (128 bits each
  direction)
• Drop Probability Increases With Traffic
• For a given Traffic Rate, Drop Probability
  Increases as Buffer Size Goes Down

31
NoC Cost Scalability vs. Alternatives

• NoC
• Non-Segmented
• Bus (NS-Bus)
• Segmented Bus (S-Bus)
• Point-To-Point (PTP)

32
NoC Cost Scalability vs. Alternatives
33
Mapping Application
Design entry Set of communicating tasks

• The flowchart illustrates basic steps required
  to map a given set of communication tasks into a
  code for NoC system

34
Applications for NOC

• Multistandard terminal
• Next generation base station
• Simulation of human brain
• Virtual reality creation
• Telepresence
• Holodeck (Star Trek)
• Purpose of Life (Hitch Hikers Guide to Galaxy)
• Simulation of universe
• Commercial operating system -)

Piece of cake
Realistic applications
Maybe not even for NOC
Real challenges for every archtitecture
35
Outline

• Motivation - Shared Medium Networks in SoC
  communication
• Network On Chip (NoC) an obvious alternative
• OSI Layered Model in NoC
• Few NoC Results
• Challenges and Research Avenues in NoC
• Summary

36
Research Avenues

• Submicron Wires / Links
• Interface study (GALS)
• Area and Power Issues
• Topology (Interconnect structure)
• Traffic management and routing protocols
• Re-configurability Concept of re-use, modularity
• Application Mapping

37
Summary

• Reasons for a Paradigm shift
• Why NoC?
• Development of NoC systems will be a huge effort
  reuse is must
• Reliability of Network is important
• Application Mapping is a crucial issue
• Physical and power constraints are bottleneck